From: Matthew Gerlach <matthew.gerlach@xxxxxxxxxxxxxxx>
Not all FPGA designs managed by the DFL driver have a port.
In these cases, don't write the Port Access Control register
when enabling SRIOV.
Signed-off-by: Matthew Gerlach <matthew.gerlach@xxxxxxxxxxxxxxx>
Signed-off-by: Tianfei Zhang <tianfei.zhang@xxxxxxxxx>
---
drivers/fpga/dfl.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
index cfc539a656f0..a5263ac258c5 100644
--- a/drivers/fpga/dfl.c
+++ b/drivers/fpga/dfl.c
@@ -1708,6 +1708,8 @@ int dfl_fpga_cdev_config_ports_vf(struct dfl_fpga_cdev *cdev, int num_vfs)
int ret = 0, port_count = 0;
mutex_lock(&cdev->lock);
+ if (list_empty(&cdev->port_dev_list))
+ goto done;
list_for_each_entry(pdata, &cdev->port_dev_list, node) {
if (pdata->dev)
--
2.17.1
