On 09/05/13 11:29, James Hogan wrote: > If the uart clock provided to the 8250_dw driver is adjustable it may > not be set to the desired rate. Therefore if both a uart clock and a > clock frequency is specified (e.g. via device tree), try and update the > clock to match the frequency. > > Unfortunately if the resulting frequency is rounded down (which is the > default behaviour of the generic clk-divider), the 8250 core won't allow > the highest baud rate to be used, so if an explicit frequency is > specified we always report that to the 8250 core. Hi, Sorry, please ignore this patch. I've realised that a larger (e.g. non-divided) source clock can just be provided directly to the uart and it appears to have enough of an internal divider for the driver to do the right thing without changing the input clock rate, although of course that clock rate still needs setting somewhere. I'm not sure why we didn't do this all along as it gives a closer frequency anyway. Thanks James -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
