Currently, when iommu.passthrough=1 is set,
all arm smmu peripherals are bypassed. This
patch allows specific peripherals to use smmu translate.
Signed-off-by: Jay Chen <jkchen@xxxxxxxxxxxxxxxxx>
---
.../admin-guide/kernel-parameters.txt | 6 +++
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 41 +++++++++++++++++++
2 files changed, 47 insertions(+)
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index 91ba391f9b32..7ecc7a4c84d7 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -2076,6 +2076,12 @@
1 - Bypass the IOMMU for DMA.
unset - Use value of CONFIG_IOMMU_DEFAULT_PASSTHROUGH.
+ smmuv3_no_passthrough=
+ [ARM64] enable smmu for devices when iommu.passthrough=1.
+ Format: {83:00.0,84:00.0,devname}
+ 83:00.0 - the bdf for one pci devices
+ devname - the name for the platform device
+
io7= [HW] IO7 for Marvel-based Alpha systems
See comment before marvel_specify_io7 in
arch/alpha/kernel/core_marvel.c.
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index a388e318f86e..e2a57bd37f32 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -76,6 +76,8 @@ struct arm_smmu_option_prop {
DEFINE_XARRAY_ALLOC1(arm_smmu_asid_xa);
DEFINE_MUTEX(arm_smmu_asid_lock);
+char *smmuv3_nopt;
+
/*
* Special value used by SVA when a process dies, to quiesce a CD without
* disabling it.
@@ -102,6 +104,17 @@ static void parse_driver_options(struct arm_smmu_device *smmu)
} while (arm_smmu_options[++i].opt);
}
+static int __init arm_smmu_no_passthrough_setup(char *str)
+{
+ if (!str)
+ return -EINVAL;
+
+ smmuv3_nopt = str;
+
+ return 0;
+}
+__setup("smmuv3_no_passthrough=", arm_smmu_no_passthrough_setup);
+
/* Low-level queue manipulation functions */
static bool queue_has_space(struct arm_smmu_ll_queue *q, u32 n)
{
@@ -2831,6 +2844,33 @@ static int arm_smmu_dev_disable_feature(struct device *dev,
}
}
+static int arm_smmu_def_domain_type(struct device *dev)
+{
+ char *str = smmuv3_nopt;
+ const char *tmp;
+
+ if (!dev || !str)
+ return 0;
+
+ if (dev_is_pci(dev)) {
+ tmp = dev_name(dev);
+ tmp += strcspn(tmp, ":") + 1;
+ } else {
+ tmp = dev_name(dev);
+ }
+
+ while (*str) {
+ if (!strncmp(str, tmp, strlen(tmp)))
+ return IOMMU_DOMAIN_DMA;
+
+ str += strcspn(str, ",");
+ while (*str == ',')
+ str++;
+ }
+
+ return 0;
+}
+
static struct iommu_ops arm_smmu_ops = {
.capable = arm_smmu_capable,
.domain_alloc = arm_smmu_domain_alloc,
@@ -2856,6 +2896,7 @@ static struct iommu_ops arm_smmu_ops = {
.sva_unbind = arm_smmu_sva_unbind,
.sva_get_pasid = arm_smmu_sva_get_pasid,
.page_response = arm_smmu_page_response,
+ .def_domain_type = arm_smmu_def_domain_type,
.pgsize_bitmap = -1UL, /* Restricted during device attach */
.owner = THIS_MODULE,
};
--
2.27.0
