On Mon, Oct 4, 2021 at 3:34 AM Samuel Holland <samuel@xxxxxxxxxxxx> wrote:
>
> On 9/29/21 9:51 AM, Alexandre Ghiti wrote:
> > By adding a new 4th level of page table, give the possibility to 64bit
> > kernel to address 2^48 bytes of virtual address: in practice, that offers
> > 128TB of virtual address space to userspace and allows up to 64TB of
> > physical memory.
> >
> > If the underlying hardware does not support sv48, we will automatically
> > fallback to a standard 3-level page table by folding the new PUD level into
> > PGDIR level. In order to detect HW capabilities at runtime, we
> > use SATP feature that ignores writes with an unsupported mode.
> >
> > Signed-off-by: Alexandre Ghiti <alexandre.ghiti@xxxxxxxxxxxxx>
> > ---
> > arch/riscv/Kconfig | 4 +-
> > arch/riscv/include/asm/csr.h | 3 +-
> > arch/riscv/include/asm/fixmap.h | 1 +
> > arch/riscv/include/asm/kasan.h | 2 +-
> > arch/riscv/include/asm/page.h | 10 +
> > arch/riscv/include/asm/pgalloc.h | 40 ++++
> > arch/riscv/include/asm/pgtable-64.h | 108 ++++++++++-
> > arch/riscv/include/asm/pgtable.h | 13 +-
> > arch/riscv/kernel/head.S | 3 +-
> > arch/riscv/mm/context.c | 4 +-
> > arch/riscv/mm/init.c | 237 ++++++++++++++++++++----
> > arch/riscv/mm/kasan_init.c | 91 +++++++--
> > drivers/firmware/efi/libstub/efi-stub.c | 2 +
> > 13 files changed, 453 insertions(+), 65 deletions(-)
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index 13e9c4298fbc..69c5533955ed 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -149,7 +149,7 @@ config PAGE_OFFSET
> > hex
> > default 0xC0000000 if 32BIT
> > default 0x80000000 if 64BIT && !MMU
> > - default 0xffffffe000000000 if 64BIT
> > + default 0xffffc00000000000 if 64BIT
> >
> > config ARCH_FLATMEM_ENABLE
> > def_bool !NUMA
> > @@ -197,7 +197,7 @@ config FIX_EARLYCON_MEM
> >
> > config PGTABLE_LEVELS
> > int
> > - default 3 if 64BIT
> > + default 4 if 64BIT
> > default 2
> >
> > config LOCKDEP_SUPPORT
> > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> > index 87ac65696871..3fdb971c7896 100644
> > --- a/arch/riscv/include/asm/csr.h
> > +++ b/arch/riscv/include/asm/csr.h
> > @@ -40,14 +40,13 @@
> > #ifndef CONFIG_64BIT
> > #define SATP_PPN _AC(0x003FFFFF, UL)
> > #define SATP_MODE_32 _AC(0x80000000, UL)
> > -#define SATP_MODE SATP_MODE_32
> > #define SATP_ASID_BITS 9
> > #define SATP_ASID_SHIFT 22
> > #define SATP_ASID_MASK _AC(0x1FF, UL)
> > #else
> > #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL)
> > #define SATP_MODE_39 _AC(0x8000000000000000, UL)
> > -#define SATP_MODE SATP_MODE_39
> > +#define SATP_MODE_48 _AC(0x9000000000000000, UL)
> > #define SATP_ASID_BITS 16
> > #define SATP_ASID_SHIFT 44
> > #define SATP_ASID_MASK _AC(0xFFFF, UL)
> > diff --git a/arch/riscv/include/asm/fixmap.h b/arch/riscv/include/asm/fixmap.h
> > index 54cbf07fb4e9..58a718573ad6 100644
> > --- a/arch/riscv/include/asm/fixmap.h
> > +++ b/arch/riscv/include/asm/fixmap.h
> > @@ -24,6 +24,7 @@ enum fixed_addresses {
> > FIX_HOLE,
> > FIX_PTE,
> > FIX_PMD,
> > + FIX_PUD,
> > FIX_TEXT_POKE1,
> > FIX_TEXT_POKE0,
> > FIX_EARLYCON_MEM_BASE,
> > diff --git a/arch/riscv/include/asm/kasan.h b/arch/riscv/include/asm/kasan.h
> > index a2b3d9cdbc86..1dcf5fa93aa0 100644
> > --- a/arch/riscv/include/asm/kasan.h
> > +++ b/arch/riscv/include/asm/kasan.h
> > @@ -27,7 +27,7 @@
> > */
> > #define KASAN_SHADOW_SCALE_SHIFT 3
> >
> > -#define KASAN_SHADOW_SIZE (UL(1) << ((CONFIG_VA_BITS - 1) - KASAN_SHADOW_SCALE_SHIFT))
> > +#define KASAN_SHADOW_SIZE (UL(1) << ((VA_BITS - 1) - KASAN_SHADOW_SCALE_SHIFT))
>
> Does this change belong in patch 1, where you remove CONFIG_VA_BITS?
Indeed, I fixed KASAN in this version and wrongly rebased the changes.
Thanks!
Alex
>
> Regards,
> Samuel
