On Fri, Sep 17, 2021 at 5:57 AM Huacai Chen <chenhuacai@xxxxxxxxxxx> wrote: > > LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. > LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit > version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its > boot protocol LoongArch-specific interrupt controllers (similar to APIC) > are already added in the next revision of ACPI Specification (current > revision is 6.4). > > This patchset is adding basic LoongArch support in mainline kernel, we > can see a complete snapshot here: > https://github.com/loongson/linux/tree/loongarch-next > > Cross-compile tool chain to build kernel: > https://github.com/loongson/build-tools/releases/latest/download/loongarch64-clfs-20210812-cross-tools.tar.xz > > A CLFS-based Linux distro: > https://github.com/loongson/build-tools/releases/latest/download/loongarch64-clfs-system-2021-08-22.tar.bz2 > > Open-source tool chain which is under review: > https://github.com/loongson/binutils-gdb/tree/loongarch-2_37 > https://github.com/loongson/gcc/tree/loongarch-12 > https://github.com/loongson/glibc/tree/loongarch_2_34_dev > > Loongson and LoongArch documentations: > https://github.com/loongson/LoongArch-Documentation > > LoongArch-specific interrupt controllers: > https://mantis.uefi.org/mantis/view.php?id=2203 > > V1 -> V2: > 1, Add documentation patches; > 2, Restore copyright statements; > 3, Split the big header patch; > 4, Cleanup signal-related headers; > 5, Cleanup incomplete 32-bit support; > 6, Move the major PCI work to drivers/pci; > 7, Rework Loongson64 platform support; > 8, Rework lpj and __udelay()/__ndelay(); > 9, Rework page table layout config options; > 10, Rework syscall/exception/interrupt with generic entry framework; > 11, Simplify the VDSO/VSYSCALL implementation; > 12, Use generic I/O access macros and functions; > 13, Remove unaligned access emulation at present; > 14, Keep clocksource code in arch since it is the "native clocksource"; > 15, Some other minor fixes and improvements. > > V2 -> V3: > 1, Rebased on 5.15-rc1; > 2, Cleanup PCI code on V2; > 3, Support multiple msi domain; > 4, Support cacheable ioremap(); > 5, Use irq stack for interrupt handling; > 6, Adjust struct ucontext and rt_sigframe; > 7, Some other minor fixes and improvements. I see you have made a lot of progress, that looks nice. I commented on the PCI stuff already, I think that needs more work and should be split out so it does not hold up the architecture merge. Also as I commented, the series needs more review from the EFI/ACPI, signal, and module maintainers among others. It would be good if you could add more information in the patch descriptions for each patch to summarize the discussions that have led to changes or whenever you got comments but argued that the current version is necessary. Arnd
