Hi Michal, On 20.03.2013 14:55, michal.bachraty@xxxxxxxxx wrote: > Thanks for writing this driver! I have tested your si5351 clock > driver and his tuning capabilities. It works well, it generates > proper clock frequency, but when new frequency is generated, little > clock gap (1ms) is generated. Si5351 datasheet and WP claims, clock > tuning can be without gaps - > http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5350-51-Frequency-Shifting-WP.pdf > > I made some tests with Si5351A chip and I found that when tuning touch > only Multisynth registers, it can tune without gaps. There is no need > for soft PLL reset. I found also, accessing Multisynth registers is not > atomic, so there can be another frequency at output, while not all > registers are written. Writing only to one register seems to be atomic. Yeah, but limiting possible changes to the PLLs to one single register also means that you cannot offer to generate all the frequencies any more. What could probably be done is refine the algorithm so that it stays 'as close as possible' to the former values, but I'm not sure how much work that implies. Can you provide a patch against Sebastian's v3 to do that? Then it can be cleanly applied on top of the driver later. Daniel -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
