Quoting Afzal Mohammed (2013-01-23 03:48:56)
<snip>
> +static inline void da8xx_fb_clkc_enable(void)
> +{
> if (lcd_revision == LCD_VERSION_2)
> lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
> LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
> }
>
> -static inline void da8xx_fb_calc_config_clk_divider(struct da8xx_fb_par *par,
> +#ifdef CONFIG_COMMON_CLK
> +static inline int da8xx_fb_calc_config_clk_divider(struct da8xx_fb_par *par,
> + struct fb_videomode *mode)
> +{
> + int ret;
> +
> + ret = clk_set_rate(par->child_clk, PICOS2KHZ(mode->pixclock) * 1000);
> + if (IS_ERR_VALUE(ret)) {
> + dev_err(par->dev, "unable to setup pixel clock of %u ps",
> + mode->pixclock);
> + return ret;
> + }
> + da8xx_fb_clkc_enable();
It looks like you are using the legacy method to enable/disable the
clock and using the CCF basic divider to set the rate. This feels a bit
hacky to me. If you want to model your clock in CCF then you should
probably model the whole clock, not just the rate-change aspects of it.
Have you looked at the composite clock patches from Prashant? Those
might give you the divider+gate properties that you are looking for:
http://article.gmane.org/gmane.linux.kernel/1416697
Regards,
Mike
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