On Sun, Sep 10, 2023 at 04:28:57AM -0400, guoren@xxxxxxxxxx wrote: > From: Guo Ren <guoren@xxxxxxxxxxxxxxxxx> > > Cache-block prefetch instructions are HINTs to the hardware to > indicate that software intends to perform a particular type of > memory access in the near future. Enable ARCH_HAS_PREFETCHW and > improve the arch_xchg for qspinlock xchg_tail. > > Signed-off-by: Guo Ren <guoren@xxxxxxxxxxxxxxxxx> > Signed-off-by: Guo Ren <guoren@xxxxxxxxxx> > --- > arch/riscv/Kconfig | 15 +++++++++++++++ > arch/riscv/include/asm/cmpxchg.h | 4 +++- > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/include/asm/insn-def.h | 5 +++++ > arch/riscv/include/asm/processor.h | 13 +++++++++++++ > arch/riscv/kernel/cpufeature.c | 1 + > 6 files changed, 38 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index e9ae6fa232c3..2c346fe169c1 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -617,6 +617,21 @@ config RISCV_ISA_ZICBOZ > > If you don't know what to do here, say Y. > > +config RISCV_ISA_ZICBOP Even if we're not concerned with looping over blocks yet, I think we should introduce zicbop block size DT parsing at the same time we bring zicbop support to the kernel (it's just more copy+paste from zicbom and zicboz). It's a bit annoying that the CMO spec doesn't state that block sizes should be the same for m/z/p. And, the fact that m/z/p are all separate extensions leads us to needing to parse block sizes for all three, despite the fact that in practice they'll probably be the same. Thanks, drew
