On Sun, Sep 10, 2023 at 04:29:04AM -0400, guoren@xxxxxxxxxx wrote:
> From: Guo Ren <guoren@xxxxxxxxxxxxxxxxx>
>
> According to qspinlock requirements, RISC-V gives out a weak LR/SC
> forward progress guarantee which does not satisfy qspinlock. But
> many vendors could produce stronger forward guarantee LR/SC to
> ensure the xchg_tail could be finished in time on any kind of
> hart. T-HEAD is the vendor
nit: "a vendor"
> which implements strong forward
> guarantee LR/SC instruction pairs, so enable qspinlock for T-HEAD
> with errata init help.
>
> Signed-off-by: Guo Ren <guoren@xxxxxxxxxxxxxxxxx>
> Signed-off-by: Guo Ren <guoren@xxxxxxxxxx>
> ---
> arch/riscv/errata/thead/errata.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> index 751eb5a7f614..0df6a67302c0 100644
> --- a/arch/riscv/errata/thead/errata.c
> +++ b/arch/riscv/errata/thead/errata.c
> @@ -86,6 +86,13 @@ static bool errata_probe_write_once(unsigned int stage,
> return false;
> }
>
> +extern bool enable_qspinlock_key;
Oh, now I understand why it was not static before. :)
> +static void errata_probe_qspinlock(unsigned int stage)
> +{
> + if (stage == RISCV_ALTERNATIVES_BOOT)
> + enable_qspinlock_key = true;
> +}
> +
> static u32 thead_errata_probe(unsigned int stage,
> unsigned long archid, unsigned long impid)
> {
> @@ -103,6 +110,8 @@ static u32 thead_errata_probe(unsigned int stage,
> if (errata_probe_write_once(stage, archid, impid))
> cpu_req_errata |= BIT(ERRATA_THEAD_WRITE_ONCE);
>
> + errata_probe_qspinlock(stage);
> +
> return cpu_req_errata;
> }
>
So, if THEAD then enable qspinlock().
LGTM:
Reviewed-by: Leonardo Bras <leobras@xxxxxxxxxx>
> --
> 2.36.1
>
