On Fri, 22 Jul 2022, Rob Herring wrote: > > > So again, how does one get a 0 address handed out when that's not even > > > a valid region according to DT? Is there some legacy stuff that > > > ignores the bridge windows? > > > > It doesn't matter as <asm/pci.h> just sets it as a generic parameter for > > the platform, reflecting the limitation of PCI core, which in the course > > of the discussion referred was found rather infeasible to remove. The > > FU740 does not decode to PCI at 0, but another RISC-V device could. And I > > think that DT should faithfully describe hardware and not our software > > limitations. > > Let me ask this another way. When would a 0 memory or i/o address ever > work? It doesn't seem this s/w limitation has anything specific to > Risc-V. Given pci_iomap_range() rejects 0, I can't see how it could > ever work. Maybe only for legacy ISA? So should the generic defaults > just be what Risc-V is using instead of 0? Absolutely, cf.: <https://lore.kernel.org/lkml/alpine.DEB.2.21.2202260044180.25061@xxxxxxxxxxxxxxxxx/>. Maciej
