Hi Stafford, How do think add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 in openrisc? https://lore.kernel.org/linux-riscv/1617201040-83905-7-git-send-email-guoren@xxxxxxxxxx/T/#u On Wed, Mar 31, 2021 at 8:31 PM Stafford Horne <shorne@xxxxxxxxx> wrote: > > On Wed, Mar 31, 2021 at 09:23:27AM +0200, Arnd Bergmann wrote: > > On Wed, Mar 31, 2021 at 12:35 AM Stafford Horne <shorne@xxxxxxxxx> wrote: > > > > > > I just want to chime in here, there may be a better spot in the thread to > > > mention this but, for OpenRISC I did implement some generic 8/16-bit xchg code > > > which I have on my todo list somwhere to replace the other generic > > > implementations like that in mips. > > > > > > arch/openrisc/include/asm/cmpxchg.h > > > > > > The idea would be that architectures just implement these methods: > > > > > > long cmpxchg_u32(*ptr,old,new) > > > long xchg_u32(*ptr,val) > > > > > > Then the rest of the generic header would implement cmpxchg. > > > > I like the idea of generalizing it a little further. I'd suggest staying a > > little closer to the existing naming here though, as we already have > > cmpxchg() for the type-agnostic version, and cmpxchg64() for the > > fixed-length 64-bit version. > > OK. > > > I think a nice interface between architecture-specific and architecture > > independent code would be to have architectures provide > > arch_cmpxchg32()/arch_xchg32() as the most basic version, as well > > as arch_cmpxchg8()/arch_cmpxchg16()/arch_xchg8()/arch_xchg16() > > if they have instructions for those. > > Thanks for the name suggestions, it makes it easier for me. > > > The common code can then build cmpxchg16()/xchg16() on top of > > either the 16-bit or the 32-bit primitives, and build the cmpxchg()/xchg() > > wrapper around those (or alternatively we can decide to have them > > only deal with fixed-32-bit and long/pointer sized atomics). > > Yeah, that was the idea. > > -Stafford -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/
