Features:
* support specification riscv-v-spec-0.7.1.
* support basic vector extension.
* support Zvlsseg.
* support Zvamo.
* not support Zvediv as it is changing.
* fixed SLEN 128bit.
* element width support 8bit, 16bit, 32bit, 64bit.
Changelog:
v4
* remove check structure, use check function directly
* use (s->vlen / 8) as maxsz in simd_maxsz
* remove helper structure vext_ctx, pass args directly.
v3
* move check code from execution time to translation time.
* probe pages before real load or store access.
* use probe_page_check for no-fault operations in linux user mode.
* add atomic and noatomic operation for vector amo instructions.
V2
* use float16_compare{_quiet}
* only use GETPC() in outer most helper
* add ctx.ext_v Property
LIU Zhiwei (5):
target/riscv: add vector unit stride load and store instructions
target/riscv: add vector stride load and store instructions
target/riscv: add vector index load and store instructions
target/riscv: add fault-only-first unit stride load
target/riscv: add vector amo operations
target/riscv/helper.h | 218 ++++
target/riscv/insn32-64.decode | 11 +
target/riscv/insn32.decode | 67 ++
target/riscv/insn_trans/trans_rvv.inc.c | 663 +++++++++++++
target/riscv/translate.c | 2 +
target/riscv/vector_helper.c | 1203 +++++++++++++++++++++++
6 files changed, 2164 insertions(+)
--
2.23.0
