Let's talk about libc abi for sigcontext and our cpu has the vector features, so we need start the work to support stress-test. I think it's the same to andes, because andes also announced the vector processor. The linux and libc are only small part of vector ISA, let's work together :) On Mon, Jan 6, 2020 at 10:45 AM Alan Kao <alankao@xxxxxxxxxxxxx> wrote: > > Hi Guo, > > On Sun, Jan 05, 2020 at 10:52:15AM +0800, guoren@xxxxxxxxxx wrote: > > From: Guo Ren <ren_guo@xxxxxxxxx> > > > > The implementation follow the RISC-V "V" Vector Extension draft v0.8 with > > 128bit-vlen and it's based on linux-5.5-rc4. > > > > According to https://lkml.org/lkml/2019/11/22/2169, in which Paul has stated > that "we plan to only accept patches for new modules or extensions that have > been frozen or ratified by the RISC-V Foundation." > > Is v0.8 ratified enough for now? > > -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/
