The IDE proposed patches do setup of endpoints while they should focus
on root port.
These are workarounds better be discussed in
"[PATCH 00/11] PCI/TSM: Core infrastructure for PCI device security
(TDISP)"
Signed-off-by: Alexey Kardashevskiy <aik@xxxxxxx>
---
include/linux/pci-ide.h | 19 +++--
include/uapi/linux/pci_regs.h | 4 +-
drivers/pci/ide.c | 76 ++++++++++++++++----
3 files changed, 78 insertions(+), 21 deletions(-)
diff --git a/include/linux/pci-ide.h b/include/linux/pci-ide.h
index 24e08a413645..f784fb16cc88 100644
--- a/include/linux/pci-ide.h
+++ b/include/linux/pci-ide.h
@@ -8,26 +8,33 @@
#include <linux/range.h>
+enum pci_ide_flags {
+ PCI_IDE_SETUP_ROOT_PORT = BIT(0),
+ PCI_IDE_SETUP_ROOT_PORT_MEM = BIT(1),
+};
+
struct pci_ide {
int domain;
u16 devid_start;
u16 devid_end;
+ u16 rpid_start;
+ u16 rpid_end;
int stream_id;
const char *name;
int nr_mem;
struct range mem[16];
+ unsigned int dev_sel_ctl;
+ unsigned int rootport_sel_ctl;
+ enum pci_ide_flags flags;
};
void pci_ide_stream_probe(struct pci_dev *pdev, struct pci_ide *ide);
-enum pci_ide_flags {
- PCI_IDE_SETUP_ROOT_PORT = BIT(0),
-};
-
int pci_ide_stream_setup(struct pci_dev *pdev, struct pci_ide *ide,
enum pci_ide_flags flags);
-void pci_ide_stream_teardown(struct pci_dev *pdev, struct pci_ide *ide,
- enum pci_ide_flags flags);
+void pci_ide_stream_teardown(struct pci_dev *pdev, struct pci_ide *ide);
void pci_ide_enable_stream(struct pci_dev *pdev, struct pci_ide *ide);
void pci_ide_disable_stream(struct pci_dev *pdev, struct pci_ide *ide);
+int pci_ide_stream_state(struct pci_dev *pdev, struct pci_ide *ide, u32 *status, u32 *rpstatus);
+
#endif /* __PCI_IDE_H__ */
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 498c6b298186..15bd8e2b3cf5 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -1293,9 +1293,9 @@
/* Selective IDE Address Association Register Block, up to PCI_IDE_SEL_CAP_ASSOC_NUM */
#define PCI_IDE_SEL_ADDR_1(x) (20 + (x) * 12)
#define PCI_IDE_SEL_ADDR_1_VALID 0x1
-#define PCI_IDE_SEL_ADDR_1_BASE_LOW_MASK 0x000fff0
+#define PCI_IDE_SEL_ADDR_1_BASE_LOW_MASK 0x000fff00
#define PCI_IDE_SEL_ADDR_1_BASE_LOW_SHIFT 20
-#define PCI_IDE_SEL_ADDR_1_LIMIT_LOW_MASK 0xfff0000
+#define PCI_IDE_SEL_ADDR_1_LIMIT_LOW_MASK 0xfff00000
#define PCI_IDE_SEL_ADDR_1_LIMIT_LOW_SHIFT 20
/* IDE Address Association Register 2 is "Memory Limit Upper" */
/* IDE Address Association Register 3 is "Memory Base Upper" */
diff --git a/drivers/pci/ide.c b/drivers/pci/ide.c
index 500b63e149cf..3c53b27f8447 100644
--- a/drivers/pci/ide.c
+++ b/drivers/pci/ide.c
@@ -50,10 +50,10 @@ void pci_ide_init(struct pci_dev *pdev)
else
sel_ide_cap = ide_cap + PCI_IDE_LINK_STREAM;
- for (int i = 0; i < PCI_IDE_CAP_SELECTIVE_STREAMS_NUM(val); i++) {
+ for (int i = 0; i < PCI_IDE_CAP_SELECTIVE_STREAMS_NUM(val) + 1; i++) {
if (i == 0) {
pci_read_config_dword(pdev, sel_ide_cap, &val);
- nr_ide_mem = PCI_IDE_SEL_CAP_ASSOC_NUM(val);
+ nr_ide_mem = PCI_IDE_SEL_CAP_ASSOC_NUM(val) + 1;
} else {
int offset = sel_ide_offset(sel_ide_cap, i, nr_ide_mem);
@@ -118,7 +118,7 @@ void pci_set_nr_ide_streams(struct pci_host_bridge *hb, int nr)
hb->nr_ide_streams = nr;
sysfs_update_group(&hb->dev.kobj, &pci_ide_attr_group);
}
-EXPORT_SYMBOL_NS_GPL(pci_set_nr_ide_streams, PCI_IDE);
+EXPORT_SYMBOL_NS_GPL(pci_set_nr_ide_streams, "PCI_IDE");
void pci_init_host_bridge_ide(struct pci_host_bridge *hb)
{
@@ -148,6 +148,10 @@ void pci_ide_stream_probe(struct pci_dev *pdev, struct pci_ide *ide)
else
ide->devid_end = ide->devid_start;
+ /* Enable everything into the rootport by default */
+ ide->rpid_start = 0;
+ ide->rpid_end = 0xffff;
+
/* TODO: address association probing... */
}
EXPORT_SYMBOL_GPL(pci_ide_stream_probe);
@@ -160,7 +164,7 @@ static void __pci_ide_stream_teardown(struct pci_dev *pdev, struct pci_ide *ide)
pdev->nr_ide_mem);
pci_write_config_dword(pdev, pos + PCI_IDE_SEL_CTL, 0);
- for (int i = ide->nr_mem - 1; i >= 0; i--) {
+ for (int i = min(ide->nr_mem, pdev->nr_ide_mem) - 1; i >= 0; i--) {
pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_3(i), 0);
pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_2(i), 0);
pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_1(i), 0);
@@ -169,7 +173,7 @@ static void __pci_ide_stream_teardown(struct pci_dev *pdev, struct pci_ide *ide)
pci_write_config_dword(pdev, pos + PCI_IDE_SEL_RID_1, 0);
}
-static void __pci_ide_stream_setup(struct pci_dev *pdev, struct pci_ide *ide)
+static int __pci_ide_stream_setup(struct pci_dev *pdev, struct pci_ide *ide, bool mem, bool rp)
{
int pos;
u32 val;
@@ -177,14 +181,20 @@ static void __pci_ide_stream_setup(struct pci_dev *pdev, struct pci_ide *ide)
pos = sel_ide_offset(pdev->sel_ide_cap, ide->stream_id,
pdev->nr_ide_mem);
- val = FIELD_PREP(PCI_IDE_SEL_RID_1_LIMIT_MASK, ide->devid_end);
+ val = FIELD_PREP(PCI_IDE_SEL_RID_1_LIMIT_MASK, rp ? ide->rpid_end : ide->devid_end);
pci_write_config_dword(pdev, pos + PCI_IDE_SEL_RID_1, val);
val = FIELD_PREP(PCI_IDE_SEL_RID_2_VALID, 1) |
- FIELD_PREP(PCI_IDE_SEL_RID_2_BASE_MASK, ide->devid_start) |
+ FIELD_PREP(PCI_IDE_SEL_RID_2_BASE_MASK, rp ? ide->rpid_start : ide->devid_start) |
FIELD_PREP(PCI_IDE_SEL_RID_2_SEG_MASK, ide->domain);
pci_write_config_dword(pdev, pos + PCI_IDE_SEL_RID_2, val);
+ if (!mem)
+ return 0;
+
+ if (ide->nr_mem > pdev->nr_ide_mem)
+ return -EINVAL;
+
for (int i = 0; i < ide->nr_mem; i++) {
val = FIELD_PREP(PCI_IDE_SEL_ADDR_1_VALID, 1) |
FIELD_PREP(PCI_IDE_SEL_ADDR_1_BASE_LOW_MASK,
@@ -201,6 +211,8 @@ static void __pci_ide_stream_setup(struct pci_dev *pdev, struct pci_ide *ide)
val = upper_32_bits(ide->mem[i].start);
pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_3(i), val);
}
+
+ return 0;
}
/*
@@ -248,10 +260,14 @@ int pci_ide_stream_setup(struct pci_dev *pdev, struct pci_ide *ide,
goto err;
}
- __pci_ide_stream_setup(pdev, ide);
- if (flags & PCI_IDE_SETUP_ROOT_PORT)
- __pci_ide_stream_setup(rp, ide);
+ rc = __pci_ide_stream_setup(pdev, ide, true, false);
+ if (!rc && (flags & PCI_IDE_SETUP_ROOT_PORT))
+ rc = __pci_ide_stream_setup(rp, ide, !!(flags & PCI_IDE_SETUP_ROOT_PORT_MEM), true);
+
+ if (rc)
+ goto err;
+ ide->flags = flags;
return 0;
err:
for (; mem >= 0; mem--)
@@ -268,6 +284,7 @@ EXPORT_SYMBOL_GPL(pci_ide_stream_setup);
void pci_ide_enable_stream(struct pci_dev *pdev, struct pci_ide *ide)
{
+ struct pci_dev *rp = pcie_find_root_port(pdev);
int pos;
u32 val;
@@ -276,14 +293,27 @@ void pci_ide_enable_stream(struct pci_dev *pdev, struct pci_ide *ide)
val = FIELD_PREP(PCI_IDE_SEL_CTL_ID_MASK, ide->stream_id) |
FIELD_PREP(PCI_IDE_SEL_CTL_DEFAULT, 1);
+ val |= FIELD_PREP(PCI_IDE_SEL_CTL_EN, 1);
+ /* there is rootport and pdev is not it */
+ if (rp && rp != pdev)
+ val |= ide->dev_sel_ctl;
+ else
+ val |= ide->rootport_sel_ctl;
pci_write_config_dword(pdev, pos + PCI_IDE_SEL_CTL, val);
+
+ if (ide->flags & PCI_IDE_SETUP_ROOT_PORT && rp && rp != pdev)
+ pci_ide_enable_stream(rp, ide);
}
EXPORT_SYMBOL_GPL(pci_ide_enable_stream);
void pci_ide_disable_stream(struct pci_dev *pdev, struct pci_ide *ide)
{
+ struct pci_dev *rp = pcie_find_root_port(pdev);
int pos;
+ if (ide->flags & PCI_IDE_SETUP_ROOT_PORT && rp && rp != pdev)
+ pci_ide_disable_stream(rp, ide);
+
pos = sel_ide_offset(pdev->sel_ide_cap, ide->stream_id,
pdev->nr_ide_mem);
@@ -291,14 +321,13 @@ void pci_ide_disable_stream(struct pci_dev *pdev, struct pci_ide *ide)
}
EXPORT_SYMBOL_GPL(pci_ide_disable_stream);
-void pci_ide_stream_teardown(struct pci_dev *pdev, struct pci_ide *ide,
- enum pci_ide_flags flags)
+void pci_ide_stream_teardown(struct pci_dev *pdev, struct pci_ide *ide)
{
struct pci_host_bridge *hb = pci_find_host_bridge(pdev->bus);
struct pci_dev *rp = pcie_find_root_port(pdev);
__pci_ide_stream_teardown(pdev, ide);
- if (flags & PCI_IDE_SETUP_ROOT_PORT)
+ if (ide->flags & PCI_IDE_SETUP_ROOT_PORT)
__pci_ide_stream_teardown(rp, ide);
for (int i = ide->nr_mem - 1; i >= 0; i--)
@@ -309,3 +338,24 @@ void pci_ide_stream_teardown(struct pci_dev *pdev, struct pci_ide *ide,
clear_bit_unlock(ide->stream_id, hb->ide_stream_ids);
}
EXPORT_SYMBOL_GPL(pci_ide_stream_teardown);
+
+static int __pci_ide_stream_state(struct pci_dev *pdev, struct pci_ide *ide, u32 *status)
+{
+ int pos = sel_ide_offset(pdev->sel_ide_cap, ide->stream_id,
+ pdev->nr_ide_mem);
+
+ return pci_read_config_dword(pdev, pos + PCI_IDE_SEL_STS, status);
+}
+
+int pci_ide_stream_state(struct pci_dev *pdev, struct pci_ide *ide, u32 *status, u32 *rpstatus)
+{
+ int ret = __pci_ide_stream_state(pdev, ide, status);
+
+ if (!ret && ide->flags & PCI_IDE_SETUP_ROOT_PORT) {
+ struct pci_dev *rp = pcie_find_root_port(pdev);
+
+ ret = __pci_ide_stream_state(rp, ide, rpstatus);
+ }
+ return ret;
+}
+EXPORT_SYMBOL_GPL(pci_ide_stream_state);
--
2.47.1
