Zhaoxin currently uses CPUID leaf 0xC0000001 instead of VIA/Cyrix/ Centaur to represent the presence or absence of certain CPU features due to company changes. The previously occupied bits in CPUID leaf 0xC0000001 remain functional, and the unoccupied bits are used by Zhaoxin to represent some new CPU features. Zhaoxin CPUs implements the PadLock Hash Engine v2 feature on the basis of features supported by CPUID leaf 0xC0000001, which indicates that Zhaoxin CPUs support SHA384/SHA512 algorithm hardware instructions. So add two Padlock Hash Engine v2 feature flags support in cpufeatures.h Zhaoxin CPUs have implemented the SHA(Secure Hash Algorithm) as its CPU instructions, including SHA1, SHA256, SHA384 and SHA512, which conform to the Secure Hash Algorithms specified by FIPS 180-3. Zhaoxin CPU's SHA1/SHA256 implementation is compatible with VIA's SHA1/SHA256, so add Zhaoxin CPU's SHA384/SHA512 support in padlock-sha.c. v2 link is below: https://lore.kernel.org/all/20240123022852.2475-1-TonyWWang-oc@xxxxxxxxxxx/ v1 link is below: https://lore.kernel.org/all/20240116063549.3016-1-TonyWWang-oc@xxxxxxxxxxx/ --- v2->v3: - Add Zhaoxin SHA384/SHA512 support in padlock-sha v1->v2: - Make Zhaoxin SHA depends on X86 && !UML - Update MAINTAINERS for Zhaoxin SHA Tony W Wang-oc (2): x86/cpufeatures: Add CPU feature flags for Zhaoxin Hash Engine v2 crypto: Add Zhaoxin PadLock Hash Engine support for SHA384/SHA512 arch/x86/include/asm/cpufeatures.h | 4 +- drivers/crypto/Kconfig | 10 +- drivers/crypto/padlock-sha.c | 200 ++++++++++++++++++++++- tools/arch/x86/include/asm/cpufeatures.h | 4 +- 4 files changed, 208 insertions(+), 10 deletions(-) -- 2.25.1
