Convert register read/write for aead via BAM/DMA.
with this change all the crypto register configuration
will be done via BAM/DMA. This change will prepare command
descriptor for all register and write it once.
Signed-off-by: Md Sadre Alam <quic_mdalam@xxxxxxxxxxx>
---
Change in [v5]
* No change
Change in [v4]
* No change
Change in [v3]
* No change
Change in [v2]
* Added initial support to read/write crypto
register via BAM for aead
Change in [v1]
* This patch was not included in [v1]
drivers/crypto/qce/common.c | 38 ++++++++++++++++++++++---------------
1 file changed, 23 insertions(+), 15 deletions(-)
diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c
index d485762a3fdc..ff96f6ba1fc5 100644
--- a/drivers/crypto/qce/common.c
+++ b/drivers/crypto/qce/common.c
@@ -454,7 +454,9 @@ static int qce_setup_regs_aead(struct crypto_async_request *async_req)
unsigned long flags = rctx->flags;
u32 encr_cfg, auth_cfg, config, totallen;
u32 iv_last_word;
+ int ret;
+ qce_clear_bam_transaction(qce);
qce_setup_config(qce);
/* Write encryption key */
@@ -467,12 +469,12 @@ static int qce_setup_regs_aead(struct crypto_async_request *async_req)
if (IS_CCM(rctx->flags)) {
iv_last_word = enciv[enciv_words - 1];
- qce_write(qce, REG_CNTR3_IV3, iv_last_word + 1);
+ qce_write_reg_dma(qce, REG_CNTR3_IV3, iv_last_word + 1, 1);
qce_write_array(qce, REG_ENCR_CCM_INT_CNTR0, (u32 *)enciv, enciv_words);
- qce_write(qce, REG_CNTR_MASK, ~0);
- qce_write(qce, REG_CNTR_MASK0, ~0);
- qce_write(qce, REG_CNTR_MASK1, ~0);
- qce_write(qce, REG_CNTR_MASK2, ~0);
+ qce_write_reg_dma(qce, REG_CNTR_MASK, ~0, 1);
+ qce_write_reg_dma(qce, REG_CNTR_MASK0, ~0, 1);
+ qce_write_reg_dma(qce, REG_CNTR_MASK1, ~0, 1);
+ qce_write_reg_dma(qce, REG_CNTR_MASK2, ~0, 1);
}
/* Clear authentication IV and KEY registers of previous values */
@@ -508,7 +510,7 @@ static int qce_setup_regs_aead(struct crypto_async_request *async_req)
encr_cfg = qce_encr_cfg(flags, enc_keylen);
if (IS_ENCRYPT(flags))
encr_cfg |= BIT(ENCODE_SHIFT);
- qce_write(qce, REG_ENCR_SEG_CFG, encr_cfg);
+ qce_write_reg_dma(qce, REG_ENCR_SEG_CFG, encr_cfg, 1);
/* Set up AUTH_SEG_CFG */
auth_cfg = qce_auth_cfg(rctx->flags, auth_keylen, ctx->authsize);
@@ -525,34 +527,40 @@ static int qce_setup_regs_aead(struct crypto_async_request *async_req)
else
auth_cfg |= AUTH_POS_BEFORE << AUTH_POS_SHIFT;
}
- qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg);
+ qce_write_reg_dma(qce, REG_AUTH_SEG_CFG, auth_cfg, 1);
totallen = rctx->cryptlen + rctx->assoclen;
/* Set the encryption size and start offset */
if (IS_CCM(rctx->flags) && IS_DECRYPT(rctx->flags))
- qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen + ctx->authsize);
+ qce_write_reg_dma(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen + ctx->authsize, 1);
else
- qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen);
- qce_write(qce, REG_ENCR_SEG_START, rctx->assoclen & 0xffff);
+ qce_write_reg_dma(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen, 1);
+ qce_write_reg_dma(qce, REG_ENCR_SEG_START, rctx->assoclen & 0xffff, 1);
/* Set the authentication size and start offset */
- qce_write(qce, REG_AUTH_SEG_SIZE, totallen);
- qce_write(qce, REG_AUTH_SEG_START, 0);
+ qce_write_reg_dma(qce, REG_AUTH_SEG_SIZE, totallen, 1);
+ qce_write_reg_dma(qce, REG_AUTH_SEG_START, 0, 1);
/* Write total length */
if (IS_CCM(rctx->flags) && IS_DECRYPT(rctx->flags))
- qce_write(qce, REG_SEG_SIZE, totallen + ctx->authsize);
+ qce_write_reg_dma(qce, REG_SEG_SIZE, totallen + ctx->authsize, 1);
else
- qce_write(qce, REG_SEG_SIZE, totallen);
+ qce_write_reg_dma(qce, REG_SEG_SIZE, totallen, 1);
/* get little endianness */
config = qce_config_reg(qce, 1);
- qce_write(qce, REG_CONFIG, config);
+ qce_write_reg_dma(qce, REG_CONFIG, config, 1);
/* Start the process */
qce_crypto_go(qce, !IS_CCM(flags));
+ ret = qce_submit_cmd_desc(qce, 0);
+ if (ret) {
+ dev_err(qce->dev, "Error in aead cmd descriptor\n");
+ return ret;
+ }
+
return 0;
}
#endif
--
2.34.1
