On Fri, Sep 13, 2024 at 05:22:09PM +0200, Jason A. Donenfeld wrote: > On Fri, Sep 13, 2024 at 05:13:28PM +0200, Jason A. Donenfeld wrote: > > On Fri, Sep 13, 2024 at 03:05:43PM +0200, Heiko Carstens wrote: > > > The vdso testcases vdso_test_getrandom and vdso_test_chacha pass. > > > > I'm trying to cross compile this but I'm getting: > > > > CC vdso_test_chacha > > /home/zx2c4/Projects/random-linux/tools/testing/selftests/../../../tools/arch/s390/vdso/vgetrandom-chacha.S: Assembler messages: > > /home/zx2c4/Projects/random-linux/tools/testing/selftests/../../../tools/arch/s390/vdso/vgetrandom-chacha.S:147: Error: Unrecognized opcode: `alsih' > > > > Any idea what's up? > > Looks like I needed `-march=arch9`. I can potentially rebuild my > toolchains to do this by default, though, if that's a normal thing to > have and this is just my toolchain being crappy. Or, if it's not a > normal thing to have, do we need to add it to the selftests Makefile? That needs to be fixed differently, since the kernel build would also fail when building for z10. Could you squash the below fix into this patch, please? That way the compiler will still generate the correct code even if compiled with a lower march flag. There is already a guard in place (test_facility()), which prevents that this code will be executed if the machine does not know the instruction. So for the kernel itself including the vdso code, everything is correct now. But similar checks are missing within vdso_test_chacha.c. I'll provide something for that, so that the test case will be skipped if the required instructions are missing, but not today. diff --git a/arch/s390/kernel/vdso64/vgetrandom-chacha.S b/arch/s390/kernel/vdso64/vgetrandom-chacha.S index ecd44cf0eaba..d802b0a96f41 100644 --- a/arch/s390/kernel/vdso64/vgetrandom-chacha.S +++ b/arch/s390/kernel/vdso64/vgetrandom-chacha.S @@ -144,7 +144,8 @@ SYM_FUNC_START(__arch_chacha20_blocks_nostack) .Lstoredone: /* ++COPY3.COUNTER */ - alsih %r3,1 + /* alsih %r3,1 */ + .insn rilu,0xcc0a00000000,%r3,1 alcr %r3,%r1 VLVGG COPY3,%r3,0
