Re: [PATCH v4 1/4] LoongArch: vDSO: Wire up getrandom() vDSO implementation

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On Tue, Aug 27, 2024 at 10:26:53PM +0800, Xi Ruoyao wrote:
> > And then use addi.w here with the integer literals instead?
> 
> LoongArch addi.w can only handle 12-bit signed immediate values (such a
> limitation is very common in RISC machines).  On my processor I can
> avoid using a register to materialize the constant with addu16i.d +
> addu12i.w + addi.w.  But there would be 3 instructions, and addu12i.w is
> a part of the Loongson Binary Translation extension which is not
> available on some processors.  Also LBT isn't intended for general use,
> so most LBT instructions have a lower throughput than the basic
> instructions.

Very interesting, thanks for the explanation.

Jason




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