On Wed, Jul 03, 2024 at 06:45:00AM +0200, Krzysztof Kozlowski wrote: > On 03/07/2024 05:56, Tengfei Fan wrote: > > Introduce support for the QCS9100 SoC device tree (DTSI) and the > > QCS9100 RIDE board DTS. The QCS9100 is a variant of the SA8775p. > > While the QCS9100 platform is still in the early design stage, the > > QCS9100 RIDE board is identical to the SA8775p RIDE board, except it > > mounts the QCS9100 SoC instead of the SA8775p SoC. > > The same huge patchset, to huge number of recipients was sent twice. > First, sorry, this is way too big. Second, it has way too many > recipients, but this is partially a result of first point. Only > partially because you put here dozen of totally unrelated emails. Sorry, > that does not make even sense. See form letter at the end how this > works. Third, sending it to everyone twice is a way to annoy them off > twice... Fourth, > > Please split your work and do not cc dozen of unrelated folks. One of the extra recipients is cos that of that patch I sent adding the cache bindings to the cache entry, forgetting that that would CC the riscv list on all cache bindings. I modified that patch to drop the riscv list from the entry. Cheers, Conor.
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