On Tue, May 21, 2024 at 07:22:02PM +0200, Borislav Petkov wrote:
> + Herbert as an FYI that I'll pick up this one and the next for 6.10 as
> it is a fix for a regression that got discovered.
>
> Thx.
>
> On Mon, May 20, 2024 at 03:45:32PM -0700, Tony Luck wrote:
> > New CPU #defines encode vendor and family as well as model.
> >
> > Signed-off-by: Tony Luck <tony.luck@xxxxxxxxx>
> > ---
> > arch/x86/crypto/aesni-intel_glue.c | 16 ++++++++--------
> > 1 file changed, 8 insertions(+), 8 deletions(-)
> >
> > diff --git a/arch/x86/crypto/aesni-intel_glue.c b/arch/x86/crypto/aesni-intel_glue.c
> > index 5b25d2a58aeb..ef031655b2d3 100644
> > --- a/arch/x86/crypto/aesni-intel_glue.c
> > +++ b/arch/x86/crypto/aesni-intel_glue.c
> > @@ -1223,14 +1223,14 @@ DEFINE_XTS_ALG(vaes_avx10_512, "xts-aes-vaes-avx10_512", 800);
> > * implementation with ymm registers (256-bit vectors) will be used instead.
> > */
> > static const struct x86_cpu_id zmm_exclusion_list[] = {
> > - { .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_SKYLAKE_X },
> > - { .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_X },
> > - { .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_D },
> > - { .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE },
> > - { .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_L },
> > - { .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_NNPI },
> > - { .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_TIGERLAKE_L },
> > - { .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_TIGERLAKE },
> > + X86_MATCH_VFM(INTEL_SKYLAKE_X, 0),
> > + X86_MATCH_VFM(INTEL_ICELAKE_X, 0),
> > + X86_MATCH_VFM(INTEL_ICELAKE_D, 0),
> > + X86_MATCH_VFM(INTEL_ICELAKE, 0),
> > + X86_MATCH_VFM(INTEL_ICELAKE_L, 0),
> > + X86_MATCH_VFM(INTEL_ICELAKE_NNPI, 0),
> > + X86_MATCH_VFM(INTEL_TIGERLAKE_L, 0),
> > + X86_MATCH_VFM(INTEL_TIGERLAKE, 0),
> > /* Allow Rocket Lake and later, and Sapphire Rapids and later. */
> > /* Also allow AMD CPUs (starting with Zen 4, the first with AVX-512). */
> > {},
> > --
Reviewed-by: Eric Biggers <ebiggers@xxxxxxxxxx>
- Eric
