Hi Jerry! On Mon, Nov 20, 2023 at 10:55:15AM +0800, Jerry Shih wrote: > >> +# - RV64I > >> +# - RISC-V Vector ('V') with VLEN >= 128 > >> +# - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb') > >> +# - RISC-V Zicclsm(Main memory supports misaligned loads/stores) > > > > How is the presence of the Zicclsm extension guaranteed? > > > > - Eric > > I have the addition extension parser for `Zicclsm` in the v2 patch set. First, I can see your updated patchset at branch "dev/jerrys/vector-crypto-upstream-v2" of https://github.com/JerryShih/linux, but I haven't seen it on the mailing list yet. Are you planning to send it out? Second, with your updated patchset, I'm not seeing any of the RISC-V optimized algorithms be registered when I boot the kernel in QEMU. This is caused by the new check 'riscv_isa_extension_available(NULL, ZICCLSM)' not passing. Is checking for "Zicclsm" the correct way to determine whether unaligned memory accesses are supported? I'm using 'qemu-system-riscv64 -cpu max -machine virt', with the very latest QEMU commit (af9264da80073435), so it should have all the CPU features. - Eric