Signed-off-by: shwetar <shwetar@xxxxxxxxxxxxxxx>
Signed-off-by: Pavitrakumar M <pavitrakumarm@xxxxxxxxxxxxxxx>
Acked-by: Ruud Derwig <Ruud.Derwig@xxxxxxxxxxxx>
---
arch/arm64/boot/dts/xilinx/Makefile | 3 ++
.../arm64/boot/dts/xilinx/snps-dwc-spacc.dtso | 35 +++++++++++++++++++
2 files changed, 38 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/snps-dwc-spacc.dtso
diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
index 5e40c0b4fa0a..d947dab02516 100644
--- a/arch/arm64/boot/dts/xilinx/Makefile
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -21,6 +21,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu1275-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA.dtb
+
zynqmp-sm-k26-revA-sck-kv-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo
zynqmp-sm-k26-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo
zynqmp-smk-k26-revA-sck-kv-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo
@@ -30,3 +31,5 @@ zynqmp-sm-k26-revA-sck-kr-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-
zynqmp-sm-k26-revA-sck-kr-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo
zynqmp-smk-k26-revA-sck-kr-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revA.dtbo
zynqmp-smk-k26-revA-sck-kr-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo
+
+zynqmp-zcu104-revC-snps-dwc-spacc-dtbs := zynqmp-zcu104-revC.dtb snps-dwc-spacc.dtbo
diff --git a/arch/arm64/boot/dts/xilinx/snps-dwc-spacc.dtso b/arch/arm64/boot/dts/xilinx/snps-dwc-spacc.dtso
new file mode 100644
index 000000000000..7ba7fbd769d2
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/snps-dwc-spacc.dtso
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Synopsys DWC SPAcc
+ *
+ * (C) Copyright 2023 Synopsys
+ *
+ * Ruud Derwig <Ruud.Derwig@xxxxxxxxxxxx>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ fragment@0 {
+ target = <&amba>;
+
+ overlay1: __overlay__ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ dwc_spacc: spacc@400000000 {
+ compatible = "snps-dwc-spacc";
+ reg = /bits/ 64 <0x400000000 0x3FFFF>;
+ interrupts = <0 89 4>;
+ interrupt-parent = <&gic>;
+ clock-names = "ref_clk";
+ spacc_priority = <0>;
+ spacc_index = <0>;
+ };
+ };
+ };
+};
--
2.25.1
