Charlie Jenkins <charlie@xxxxxxxxxxxx> writes: >> +.macro VROR REG BITS TMPREG >> + vmv.v.v \TMPREG, \REG >> + vsrl.vi \REG, \REG, \BITS >> + vsll.vi \TMPREG, \TMPREG, 32-\BITS >> + vor.vv \REG, \REG, \TMPREG >> +.endm > > This seems like it would be a good candidate to use the Zvkb extension > that has vector rotate [1]. It would be a pain to use because you need > two versions of the roundloop, but you could get away with 1 extra > branch/nop and save 3 instructions per VROR which looks like it happens > 8*10 times, so 239 fewer instructions. > > [1] https://github.com/riscv/riscv-crypto/releases Indeed! Thanks! Björn
