The field `idle_filter` in the CPM_PM_FW_INIT CSR determines
after how much time the device will be transition to a low power
state if it is detected to be idle.
This value is managed by FW regardless of what SW sets.
Make the `idle_filter` field in the FW interface as reserved.
Signed-off-by: Lucas Segarra Fernandez <lucas.segarra.fernandez@xxxxxxxxx>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@xxxxxxxxx>
---
drivers/crypto/intel/qat/qat_common/adf_admin.c | 12 +-----------
drivers/crypto/intel/qat/qat_common/adf_common_drv.h | 2 +-
drivers/crypto/intel/qat/qat_common/adf_gen4_pm.c | 2 +-
.../intel/qat/qat_common/icp_qat_fw_init_admin.h | 2 +-
4 files changed, 4 insertions(+), 14 deletions(-)
diff --git a/drivers/crypto/intel/qat/qat_common/adf_admin.c b/drivers/crypto/intel/qat/qat_common/adf_admin.c
index 4a671004cbcf..44c54321c8fe 100644
--- a/drivers/crypto/intel/qat/qat_common/adf_admin.c
+++ b/drivers/crypto/intel/qat/qat_common/adf_admin.c
@@ -284,22 +284,13 @@ EXPORT_SYMBOL_GPL(adf_send_admin_init);
/**
* adf_init_admin_pm() - Function sends PM init message to FW
* @accel_dev: Pointer to acceleration device.
- * @idle_delay: QAT HW idle time before power gating is initiated.
- * 000 - 64us
- * 001 - 128us
- * 010 - 256us
- * 011 - 512us
- * 100 - 1ms
- * 101 - 2ms
- * 110 - 4ms
- * 111 - 8ms
*
* Function sends to the FW the admin init message for the PM state
* configuration.
*
* Return: 0 on success, error code otherwise.
*/
-int adf_init_admin_pm(struct adf_accel_dev *accel_dev, u32 idle_delay)
+int adf_init_admin_pm(struct adf_accel_dev *accel_dev)
{
struct adf_hw_device_data *hw_data = accel_dev->hw_device;
struct icp_qat_fw_init_admin_resp resp = {0};
@@ -312,7 +303,6 @@ int adf_init_admin_pm(struct adf_accel_dev *accel_dev, u32 idle_delay)
}
req.cmd_id = ICP_QAT_FW_PM_STATE_CONFIG;
- req.idle_filter = idle_delay;
return adf_send_admin(accel_dev, &req, &resp, ae_mask);
}
diff --git a/drivers/crypto/intel/qat/qat_common/adf_common_drv.h b/drivers/crypto/intel/qat/qat_common/adf_common_drv.h
index 40e7ea95528b..15ef47958b2a 100644
--- a/drivers/crypto/intel/qat/qat_common/adf_common_drv.h
+++ b/drivers/crypto/intel/qat/qat_common/adf_common_drv.h
@@ -95,7 +95,7 @@ int adf_init_admin_comms(struct adf_accel_dev *accel_dev);
void adf_exit_admin_comms(struct adf_accel_dev *accel_dev);
int adf_send_admin_init(struct adf_accel_dev *accel_dev);
int adf_get_ae_fw_counters(struct adf_accel_dev *accel_dev, u16 ae, u64 *reqs, u64 *resps);
-int adf_init_admin_pm(struct adf_accel_dev *accel_dev, u32 idle_delay);
+int adf_init_admin_pm(struct adf_accel_dev *accel_dev);
int adf_send_admin_tim_sync(struct adf_accel_dev *accel_dev, u32 cnt);
int adf_init_arb(struct adf_accel_dev *accel_dev);
void adf_exit_arb(struct adf_accel_dev *accel_dev);
diff --git a/drivers/crypto/intel/qat/qat_common/adf_gen4_pm.c b/drivers/crypto/intel/qat/qat_common/adf_gen4_pm.c
index 34c6cd8e27c0..dd9d3b4ca8b1 100644
--- a/drivers/crypto/intel/qat/qat_common/adf_gen4_pm.c
+++ b/drivers/crypto/intel/qat/qat_common/adf_gen4_pm.c
@@ -125,7 +125,7 @@ int adf_gen4_enable_pm(struct adf_accel_dev *accel_dev)
int ret;
u32 val;
- ret = adf_init_admin_pm(accel_dev, ADF_GEN4_PM_DEFAULT_IDLE_FILTER);
+ ret = adf_init_admin_pm(accel_dev);
if (ret)
return ret;
diff --git a/drivers/crypto/intel/qat/qat_common/icp_qat_fw_init_admin.h b/drivers/crypto/intel/qat/qat_common/icp_qat_fw_init_admin.h
index d853c9242acf..7233b62cfaa7 100644
--- a/drivers/crypto/intel/qat/qat_common/icp_qat_fw_init_admin.h
+++ b/drivers/crypto/intel/qat/qat_common/icp_qat_fw_init_admin.h
@@ -40,7 +40,7 @@ struct icp_qat_fw_init_admin_req {
struct {
__u32 int_timer_ticks;
};
- __u32 idle_filter;
+ __u32 resrvd5;
};
__u32 resrvd4;
base-commit: c2c7c99da874ec3201aabdfe04be8e26a684b3f5
--
2.39.2
