On 26.05.2023 21:22, Bhupesh Sharma wrote:
> From: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
>
> Add crypto engine (CE) and CE BAM related nodes and definitions
> for the SM8450 SoC.
>
> Tested-by: Anders Roxell <anders.roxell@xxxxxxxxxx>
> Tested-by: Linux Kernel Functional Testing <lkft@xxxxxxxxxx>
> Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
> [Bhupesh: Corrected the compatible list]
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@xxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 28 ++++++++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index 7f193802a7c4..1642daea9624 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -4173,6 +4173,34 @@ ufs_mem_phy_lanes: phy@1d87400 {
> };
> };
>
> + cryptobam: dma-controller@1dc4000 {
> + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
> + reg = <0 0x01dc4000 0 0x28000>;
> + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
> + #dma-cells = <1>;
> + qcom,ee = <0>;
> + qcom,controlled-remotely;
> + iommus = <&apps_smmu 0x584 0x11>,
> + <&apps_smmu 0x588 0x0>,
> + <&apps_smmu 0x598 0x5>,
Does mapping 0x598 with and without the SMR mask make sense?
(this is a genuine question, I have no idea but would be leaning
on the side of no)
Konrad
> + <&apps_smmu 0x59a 0x0>,
> + <&apps_smmu 0x59f 0x0>;
> + };
> +
> + crypto: crypto@1de0000 {
> + compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce";
> + reg = <0 0x01dfa000 0 0x6000>;
> + dmas = <&cryptobam 4>, <&cryptobam 5>;
> + dma-names = "rx", "tx";
> + iommus = <&apps_smmu 0x584 0x11>,
> + <&apps_smmu 0x588 0x0>,
> + <&apps_smmu 0x598 0x5>,
> + <&apps_smmu 0x59a 0x0>,
> + <&apps_smmu 0x59f 0x0>;
> + interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "memory";
> + };
> +
> sdhc_2: mmc@8804000 {
> compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5";
> reg = <0 0x08804000 0 0x1000>;
