Hi Vladimir,
On 2/9/23 12:07 AM, Vladimir Zapolskiy wrote:
Add description of QCE and its corresponding BAM DMA IPs on SM8250 SoC.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@xxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index e59c16f74d17..d8698d18223e 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2215,6 +2215,30 @@ ufs_mem_phy_lanes: phy@1d87400 {
};
};
+ cryptobam: dma-controller@1dc4000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x0 0x01dc4000 0x0 0x24000>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ qcom,controlled-remotely;
+ num-channels = <8>;
+ qcom,num-ees = <2>;
+ iommus = <&apps_smmu 0x586 0x11>,
+ <&apps_smmu 0x596 0x11>;
+ };
+
+ crypto: crypto@1dfa000 {
+ compatible = "qcom,sm8250-qce", "qcom,sm8150-qce";
+ reg = <0x0 0x01dfa000 0x0 0x6000>;
+ dmas = <&cryptobam 6>, <&cryptobam 7>;
+ dma-names = "rx", "tx";
+ interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>;
+ interconnect-names = "memory";
+ iommus = <&apps_smmu 0x586 0x11>,
+ <&apps_smmu 0x596 0x11>;
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x40000>;
This patch was part of the v7 arm64 dts fixes I sent out - see [1].
Probably you can use it as a base and make the changes (interconnect
property for the BAM DMA node and qce-compatible names) directly there
and include it in your patch series.
[1].
https://lore.kernel.org/linux-arm-msm/20220921045602.1462007-3-bhupesh.sharma@xxxxxxxxxx/
Thanks,
Bhupesh
