On 1/26/23 05:52, Jann Horn wrote: > On Wed, Jan 25, 2023 at 4:30 PM Dave Hansen <dave.hansen@xxxxxxxxx> wrote: >> Translating from Intel-speak: Intel thinks that DOITM purely a way to >> make the CPU run slower if you haven't already written code specifically >> to mitigate timing side channels. All pain, no gain. >> >> The kernel as a whole is not written that way. > > The kernel as a whole also doesn't really use the FPU registers for > anything other than checksumming and cryptography and stuff like that > (it's disabled in the compiler flags because the FPU registers > normally contain userspace state that must not be clobbered). The > instructions listed on that Intel help page are all weird PM* and VP* > arithmetic instructions that can't be generated from C code in the > kernel (except for weird subsystems in which every function is only > callable in kernel-FPU-enabled mode and the compiler is set to enable > FPU instruction generation, by which I mean amdgpu). Maybe I'm totally missing something, but I thought the scope here was the "non-data operand independent timing behavior for the listed instructions" referenced here: > https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/best-practices/data-operand-independent-timing-isa-guidance.html where the "listed instructions" is this list: > https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/resources/data-operand-independent-timing-instructions.html For example, that includes XOR with the 0x31 and 0x81 opcodes which there are plenty of in the kernel. That's a bit wider scope than the crazy instructions like VPLZCNTD. The crazy instructions list that I _think_ you were grepping for is the "Instructions That May Exhibit MCDT Behavior". That's also a fun one, but it is more narrow than the DOITM list.
