On Tue, Jan 10, 2023 at 02:50:31PM +0100, Vincent Whitchurch wrote:
>
> @@ -2216,6 +2220,14 @@ static void artpec6_crypto_complete_aead(struct crypto_async_request *req)
>
> static void artpec6_crypto_complete_hash(struct crypto_async_request *req)
> {
> + struct ahash_request *areq = container_of(req, struct ahash_request, base);
> + struct artpec6_hash_request_context *ctx = ahash_request_ctx(areq);
> + struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
> + size_t digestsize = crypto_ahash_digestsize(ahash);
> +
> + if (ctx->hash_flags & HASH_FLAG_FINALIZED)
> + memcpy(areq->result, ctx->digeststate, digestsize);
> +
I was just looking through the driver and digeststate does not
appear to be aligned to the DMA cacheline, should it be?
Thanks,
--
Email: Herbert Xu <herbert@xxxxxxxxxxxxxxxxxxx>
Home Page: http://gondor.apana.org.au/~herbert/
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