On Thu, Dec 01, 2022 at 06:17:26AM +0000, JiaJie Ho wrote: > > -----Original Message----- > > From: Conor.Dooley@xxxxxxxxxxxxx <Conor.Dooley@xxxxxxxxxxxxx> > > Hey Jia Jie Ho, > > > > On 30/11/2022 05:52, Jia Jie Ho wrote: > > > [You don't often get email from jiajie.ho@xxxxxxxxxxxxxxxx. Learn why > > > this is important at https://aka.ms/LearnAboutSenderIdentification ] > > > > > > EXTERNAL EMAIL: Do not click links or open attachments unless you know > > > the content is safe > > > > > > Adding StarFive crypto IP and DMA controller node to VisionFive 2 SoC. > > > > > > Signed-off-by: Jia Jie Ho <jiajie.ho@xxxxxxxxxxxxxxxx> > > > Signed-off-by: Huan Feng <huan.feng@xxxxxxxxxxxxxxxx> > > > > Out of curiosity, what was Huan Feng's contribution to this patch? > > Did they co-develop it, or is there some other reason? > > > Hi Conor, > Yes, Huan Feng co-developed this driver. In that case, the SoB block should look like: Co-developed-by: Huan Feng <huan.feng@xxxxxxxxxxxxxxxx> Signed-off-by: Huan Feng <huan.feng@xxxxxxxxxxxxxxxx> Signed-off-by: Jia Jie Ho <jiajie.ho@xxxxxxxxxxxxxxxx> Similarly for any other patches they may have co-developed :) > > > > > > diff --git > > > a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts > > > b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts > > > index 450e920236a5..da2aa4d597f3 100644 > > > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts > > > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts > > > @@ -115,3 +115,11 @@ &tdm_ext { > > > &mclk_ext { > > > clock-frequency = <49152000>; > > > }; > > > + > > > +&sec_dma { > > > + status = "okay"; > > > +}; > > > + > > > +&crypto { > > > + status = "okay"; > > > +}; > > > > In what scenario would you not want to have these enabled? > These drivers are always enabled. > Is everything ok with the dts node entries? If the hardware is always present, why not drop the "disabled" in jh7110.dtsi & these two entries marking them as "okay" in the .dts? > > > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi > > > b/arch/riscv/boot/dts/starfive/jh7110.dtsi > > > index 4ac159d79d66..745a5650882c 100644 > > > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > > > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > > > @@ -455,5 +455,41 @@ uart5: serial@12020000 { > > > reg-shift = <2>; > > > status = "disabled"; > > > }; > > > + > > > + sec_dma: sec_dma@16008000 { > > > + status = "disabled"; > > > + }; > > > + > > > + crypto: crypto@16000000 { > > > + status = "disabled"; > > > + }; > > > }; > > > }; Thanks, Conor.
