Drop the homebrewn uint64 support, the kernel has a u64 type
that works just fine so we use that instead.
Signed-off-by: Linus Walleij <linus.walleij@xxxxxxxxxx>
---
ChangeLog v2->v3:
- Rebased on v6.0-rc1
ChangeLog v1->v2:
- No changes
---
drivers/crypto/ux500/hash/hash_alg.h | 19 ++----------------
drivers/crypto/ux500/hash/hash_core.c | 28 ++++-----------------------
2 files changed, 6 insertions(+), 41 deletions(-)
diff --git a/drivers/crypto/ux500/hash/hash_alg.h b/drivers/crypto/ux500/hash/hash_alg.h
index 05f0b0221a13..6a610c83e63d 100644
--- a/drivers/crypto/ux500/hash/hash_alg.h
+++ b/drivers/crypto/ux500/hash/hash_alg.h
@@ -16,9 +16,6 @@
#define HASH_DMA_PERFORMANCE_MIN_SIZE 1024
#define HASH_BYTES_PER_WORD 4
-/* Maximum value of the length's high word */
-#define HASH_HIGH_WORD_MAX_VAL 0xFFFFFFFFUL
-
/* Power on Reset values HASH registers */
#define HASH_RESET_CR_VALUE 0x0
#define HASH_RESET_STR_VALUE 0x0
@@ -135,18 +132,6 @@ enum hash_mode {
HASH_MODE_DMA
};
-/**
- * struct uint64 - Structure to handle 64 bits integers.
- * @high_word: Most significant bits.
- * @low_word: Least significant bits.
- *
- * Used to handle 64 bits integers.
- */
-struct uint64 {
- u32 high_word;
- u32 low_word;
-};
-
/**
* struct hash_register - Contains all registers in ux500 hash hardware.
* @cr: HASH control register (0x000).
@@ -227,7 +212,7 @@ struct hash_state {
u32 csfull;
u32 csdatain;
u32 buffer[HASH_BLOCK_SIZE / sizeof(u32)];
- struct uint64 length;
+ u64 length;
u8 index;
bool dma_mode;
bool hw_initialized;
@@ -342,7 +327,7 @@ struct hash_ctx {
*/
struct hash_req_ctx {
u32 buffer[HASH_BLOCK_SIZE / sizeof(u32)];
- struct uint64 length;
+ u64 length;
u8 index;
bool dma_mode;
bool hw_initialized;
diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index c8771839ec8e..5fe0720cb1f5 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -449,8 +449,7 @@ static int ux500_hash_init(struct ahash_request *req)
ctx->keylen = 0;
req_ctx->index = 0;
- req_ctx->length.low_word = 0;
- req_ctx->length.high_word = 0;
+ req_ctx->length = 0;
req_ctx->hw_initialized = false;
if (hash_mode == HASH_MODE_DMA) {
if (req->nbytes < HASH_DMA_ALIGN_SIZE) {
@@ -545,23 +544,6 @@ static void hash_messagepad(struct hash_device_data *device_data,
cpu_relax();
}
-/**
- * hash_incrementlength - Increments the length of the current message.
- * @ctx: Hash context
- * @incr: Length of message processed already
- *
- * Overflow cannot occur, because conditions for overflow are checked in
- * hash_hw_update.
- */
-static void hash_incrementlength(struct hash_req_ctx *ctx, u32 incr)
-{
- ctx->length.low_word += incr;
-
- /* Check for wrap-around */
- if (ctx->length.low_word < incr)
- ctx->length.high_word++;
-}
-
/**
* hash_setconfiguration - Sets the required configuration for the hash
* hardware.
@@ -709,7 +691,7 @@ static int hash_process_data(struct hash_device_data *device_data,
(const u32 *)buffer,
HASH_BLOCK_SIZE);
}
- hash_incrementlength(req_ctx, HASH_BLOCK_SIZE);
+ req_ctx->length += HASH_BLOCK_SIZE;
data_buffer += (HASH_BLOCK_SIZE - *index);
msg_length -= (HASH_BLOCK_SIZE - *index);
@@ -933,10 +915,8 @@ int hash_hw_update(struct ahash_request *req)
if (msg_length == 0)
return 0;
- /* Check if ctx->length + msg_length
- overflows */
- if (msg_length > (req_ctx->length.low_word + msg_length) &&
- req_ctx->length.high_word == HASH_HIGH_WORD_VAL_MAX) {
+ /* Check if ctx->length + msg_length overflows */
+ if ((req_ctx->length + msg_length) < msg_length) {
pr_err("%s: HASH_MSG_LENGTH_OVERFLOW!\n", __func__);
return crypto_hash_walk_done(&walk, -EPERM);
}
--
2.37.2
