On Wed, May 04, 2022 at 12:18:18AM +0000, Nathan Huckleberry wrote: > Add hardware accelerated versions of XCTR for x86-64 CPUs with AESNI > support. These implementations are modified versions of the CTR > implementations found in aesni-intel_asm.S and aes_ctrby8_avx-x86_64.S. The commit message still needs to be fixed, as I noted on v5, since there is now only one implementation being added, and aesni-intel_asm.S isn't being changed. > > More information on XCTR can be found in the HCTR2 paper: > "Length-preserving encryption with HCTR2": > https://eprint.iacr.org/2021/1441.pdf > > Signed-off-by: Nathan Huckleberry <nhuck@xxxxxxxxxx> > Reviewed-by: Ard Biesheuvel <ardb@xxxxxxxxxx> > --- > arch/x86/crypto/aes_ctrby8_avx-x86_64.S | 232 ++++++++++++++++-------- > arch/x86/crypto/aesni-intel_glue.c | 114 +++++++++++- > crypto/Kconfig | 2 +- > 3 files changed, 266 insertions(+), 82 deletions(-) Otherwise this patch looks good: Reviewed-by: Eric Biggers <ebiggers@xxxxxxxxxx> - Eric
