On Sun, May 01, 2022 at 12:34:02AM +0200, Jason A. Donenfeld wrote: > Hi Stafford, > > On Sun, May 01, 2022 at 07:11:37AM +0900, Stafford Horne wrote: > > > I was thinking about this, the reason the tick timer is returing 0 is because > > the timer is not started. It's getting initialized right after the random > > number generator. > > > > A patch like this helps to startup the timer during intial startup, but I am not > > sure its the best thing: > > > > diff --git a/arch/openrisc/kernel/head.S b/arch/openrisc/kernel/head.S > > index 15f1b38dfe03..a9b3b5614e13 100644 > > --- a/arch/openrisc/kernel/head.S > > +++ b/arch/openrisc/kernel/head.S > > @@ -521,6 +521,9 @@ _start: > > l.ori r3,r0,0x1 > > l.mtspr r0,r3,SPR_SR > > > > + l.movhi r3,hi(SPR_TTMR_CR) > > + l.mtspr r0,r3,SPR_TTMR > > + > > CLEAR_GPR(r1) > > CLEAR_GPR(r2) > > CLEAR_GPR(r3) > > Yea, great, I was thinking about doing it in assembly earlier in boot > too, but didn't know how you'd feel about that. I like this better. > > The reason I think this is a good approach is that it means the cycle > counter includes some information about how long startup takes from the > earliest stages -- which could involve probing various devices or > strange things. So enabling the timer in head.S seems good to me. > > > But I wonder: > > - Why don't any other architectures have similar issues. > > - Is there any more correct place to do an early timer kick off. > > I think most other archs (like, say, x86) have their cycle counter > enabled by default at boot time. I was surprised to see that the or1k > risc cycle counter comes disabled by default actually. > > I'll send a v9 incorporating your suggested assembly change. Thanks! -Stafford
