On Fri, Apr 15, 2022 at 01:26:48PM +0100, Maciej W. Rozycki wrote: > Hi Jason, > > > > It depends on the exact system. Some have a 32-bit high-resolution > > > counter in the chipset (arch/mips/kernel/csrc-ioasic.c) giving like 25MHz > > > resolution, some have nothing but jiffies. > > > > Alright, so there _are_ machines with no c0 cycles but with a good > > clock. Yet, 25MHz is still less than the cpu cycle, so this c0 random > > ORing trick remains useful perhaps. > > It's not much less than the CPU cycle really, given that the R3k CPUs are > clocked at up to 40MHz in the systems concerned and likewise the buggy R4k > CPUs run at up to 60MHz (and mind that their CP0 Count register increments > at half the clock rate, so the rate is up to 30MHz anyway). The overhead > of the calculation is more than that, let alone the latency and issue rate > of an uncached MMIO access to the chipset register. > > Also the systems I have in mind and that lack a counter in the chipset > actually can make use of the buggy CP0 timer, because it's only when CP0 > timer interrupts are used that the erratum matters, but they use a DS1287 > RTC interrupt instead unconditionally as the clock event (see the comment > at the bottom of arch/mips/dec/time.c). But this has not been factored in > with `can_use_mips_counter' (should it just check for `mips_hpt_frequency' > being zero perhaps, meaning the timer interrupt not being used?). > > Thomas, do you happen to know if any of the SGI systems that we support > had buggy early R4k chips? IP22 has probably seen all buggy MIPS chips produced, so yes I even own Indy/Indigo2 CPU boards with early R4k chips. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessarily a good idea. [ RFC1925, 2.3 ]
