On 08/11/2021 16:05, conor.dooley@xxxxxxxxxxxxx wrote:
> From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
>
> Add device tree bindings for the {q,}spi controller on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> ---
> .../bindings/spi/microchip,mpfs-spi.yaml | 72 +++++++++++++++++++
> 1 file changed, 72 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
>
> diff --git a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
> new file mode 100644
> index 000000000000..efed145ad029
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
> @@ -0,0 +1,72 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip MPFS {Q,}SPI Controller Device Tree Bindings
> +
> +maintainers:
> + - Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> +
> +description: |
> + This {Q,}SPI controller is found on the Microchip PolarFire SoC.
> +
> +allOf:
> + - $ref: "spi-controller.yaml#"
No need for quotes.
> +
> +properties:
> + compatible:
> + enum:
> + - microchip,mpfs-spi
> + - microsemi,ms-pf-mss-spi
> + - microchip,mpfs-qspi
> + - microsemi,ms-pf-mss-qspi
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clock-names:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 2
This does not match clock-names. Describe clocks instead. Are you really
sure your hardware can have an optional second clock?
> +
> + num-cs:
> + description: |
> + Number of chip selects used.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 1
> + maximum: 8
> + default: 8
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include "dt-bindings/clock/microchip,mpfs-clock.h"
> + #include "dt-bindings/interrupt-controller/microchip,mpfs-plic.h"
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + spi0: spi@20108000 {
> + compatible = "microchip,mpfs-spi";
> + reg = <0x0 0x20108000 0x0 0x1000>;
> + clocks = <&clkcfg CLK_SPI0>;
> + interrupt-parent = <&plic>;
> + interrupts = <PLIC_INT_SPI0>;
> + spi-max-frequency = <25000000>;
> + num-cs = <8>;
> + status = "disabled";
> + };
> + };
> +...
>
Best regards,
Krzysztof
