Hi Kai, Thank you for the patch! Yet something to improve: [auto build test ERROR on cryptodev/master] [also build test ERROR on crypto/master linux/master linus/master v5.14-rc5 next-20210812] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Kai-Ye/crypto-hisilicon-some-misc-bugfix-for-SEC-engine/20210813-102441 base: https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git master config: ia64-allmodconfig (attached as .config) compiler: ia64-linux-gcc (GCC) 10.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/3a700b467c3a65e18d9a7a2b7939c6b2fc369da7 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Kai-Ye/crypto-hisilicon-some-misc-bugfix-for-SEC-engine/20210813-102441 git checkout 3a700b467c3a65e18d9a7a2b7939c6b2fc369da7 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-10.3.0 make.cross ARCH=ia64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@xxxxxxxxx> All errors (new ones prefixed by >>): drivers/crypto/hisilicon/sec2/sec_main.c: In function 'sec_engine_init': >> drivers/crypto/hisilicon/sec2/sec_main.c:455:2: error: implicit declaration of function 'sec_get_endian'; did you mean 'sec_set_endian'? [-Werror=implicit-function-declaration] 455 | sec_get_endian(qm); | ^~~~~~~~~~~~~~ | sec_set_endian At top level: drivers/crypto/hisilicon/sec2/sec_main.c:321:13: warning: 'sec_set_endian' defined but not used [-Wunused-function] 321 | static void sec_set_endian(struct hisi_qm *qm) | ^~~~~~~~~~~~~~ cc1: some warnings being treated as errors vim +455 drivers/crypto/hisilicon/sec2/sec_main.c 405 406 static int sec_engine_init(struct hisi_qm *qm) 407 { 408 int ret; 409 u32 reg; 410 411 /* disable clock gate control before mem init */ 412 sec_disable_clock_gate(qm); 413 414 writel_relaxed(0x1, qm->io_base + SEC_MEM_START_INIT_REG); 415 416 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_MEM_INIT_DONE_REG, 417 reg, reg & 0x1, SEC_DELAY_10_US, 418 SEC_POLL_TIMEOUT_US); 419 if (ret) { 420 pci_err(qm->pdev, "fail to init sec mem\n"); 421 return ret; 422 } 423 424 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); 425 reg |= (0x1 << SEC_TRNG_EN_SHIFT); 426 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); 427 428 reg = readl_relaxed(qm->io_base + SEC_INTERFACE_USER_CTRL0_REG); 429 reg |= SEC_USER0_SMMU_NORMAL; 430 writel_relaxed(reg, qm->io_base + SEC_INTERFACE_USER_CTRL0_REG); 431 432 reg = readl_relaxed(qm->io_base + SEC_INTERFACE_USER_CTRL1_REG); 433 reg &= SEC_USER1_SMMU_MASK; 434 if (qm->use_sva && qm->ver == QM_HW_V2) 435 reg |= SEC_USER1_SMMU_SVA; 436 else 437 reg |= SEC_USER1_SMMU_NORMAL; 438 writel_relaxed(reg, qm->io_base + SEC_INTERFACE_USER_CTRL1_REG); 439 440 writel(SEC_SINGLE_PORT_MAX_TRANS, 441 qm->io_base + AM_CFG_SINGLE_PORT_MAX_TRANS); 442 443 writel(SEC_SAA_ENABLE, qm->io_base + SEC_SAA_EN_REG); 444 445 /* Enable sm4 extra mode, as ctr/ecb */ 446 writel_relaxed(SEC_BD_ERR_CHK_EN0, 447 qm->io_base + SEC_BD_ERR_CHK_EN_REG0); 448 /* Enable sm4 xts mode multiple iv */ 449 writel_relaxed(SEC_BD_ERR_CHK_EN1, 450 qm->io_base + SEC_BD_ERR_CHK_EN_REG1); 451 writel_relaxed(SEC_BD_ERR_CHK_EN3, 452 qm->io_base + SEC_BD_ERR_CHK_EN_REG3); 453 454 /* config endian */ > 455 sec_get_endian(qm); 456 457 sec_enable_clock_gate(qm); 458 459 return 0; 460 } 461 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx
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