Add support for UFS ICE (Qualcomm Inline Crypto Engine) in
sm8150 SoC dts.
I tested this on SA8155p-adp board, which is a publicly
available development board that uses the sa8155p Qualcomm
Snapdragon SoC. SA8155p platform is similar to the SM8150,
so use this as base for now.
I tested the UFS ICE feature using 'fscrypt' test utility.
Cc: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx>
Cc: Eric Biggers <ebiggers@xxxxxxxxxx>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@xxxxxxxxxx>
---
Here are some details on how, I tested the UFS ICE feature
on SA8155p-adp:
1. Build a kernel with:
CONFIG_BLK_INLINE_ENCRYPTION=y
CONFIG_FS_ENCRYPTION=y
CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y
CONFIG_SCSI_UFS_CRYPTO=y
2. Create a filesystem with 'mkfs.ext4 -O encrypt'
3. Mount the filesystem with '-o inlinecrypt'
4. Create an encrypted directory and copy some files into it.
5. Unmount the filesystem, and mount it *without* '-o inlinecrypt'.
6. Verify that the files match the originals.
7. Also test the fscrypt lock / unlock combinations.
arch/arm64/boot/dts/qcom/sm8150.dtsi | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 163eb430eb1e..c4e3939a1cb9 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -1016,7 +1016,9 @@ system-cache-controller@9200000 {
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
- reg = <0 0x01d84000 0 0x2500>;
+ reg = <0 0x01d84000 0 0x2500>,
+ <0 0x01d90000 0 0x8000>;
+ reg-names = "std", "ice";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs_mem_phy_lanes>;
phy-names = "ufsphy";
@@ -1035,7 +1037,8 @@ ufs_mem_hc: ufshc@1d84000 {
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
- "rx_lane1_sync_clk";
+ "rx_lane1_sync_clk",
+ "ice_core_clk";
clocks =
<&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
@@ -1044,7 +1047,8 @@ ufs_mem_hc: ufshc@1d84000 {
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
- <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
+ <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
freq-table-hz =
<37500000 300000000>,
<0 0>,
@@ -1053,7 +1057,8 @@ ufs_mem_hc: ufshc@1d84000 {
<0 0>,
<0 0>,
<0 0>,
- <0 0>;
+ <0 0>,
+ <0 300000000>;
status = "disabled";
};
--
2.31.1
