Hi Hui, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on cryptodev/master] [also build test WARNING on crypto/master v5.13-rc1 next-20210510] [cannot apply to sparc-next/master] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Hui-Tang/crypto-hisilicon-hpre-fix-coding-style/20210510-171126 base: https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git master config: ia64-allmodconfig (attached as .config) compiler: ia64-linux-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/7cb1823201d8d0f6951e6b15b9d46ce81b601597 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Hui-Tang/crypto-hisilicon-hpre-fix-coding-style/20210510-171126 git checkout 7cb1823201d8d0f6951e6b15b9d46ce81b601597 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross W=1 ARCH=ia64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@xxxxxxxxx> All warnings (new ones prefixed by >>): >> drivers/crypto/hisilicon/hpre/hpre_main.c:78: warning: "HPRE_QM_USR_CFG_MASK" redefined 78 | #define HPRE_QM_USR_CFG_MASK GENMASK(31, 1) | drivers/crypto/hisilicon/hpre/hpre_main.c:72: note: this is the location of the previous definition 72 | #define HPRE_QM_USR_CFG_MASK 0xfffffffe | >> drivers/crypto/hisilicon/hpre/hpre_main.c:79: warning: "HPRE_QM_AXI_CFG_MASK" redefined 79 | #define HPRE_QM_AXI_CFG_MASK GENMASK(15, 0) | drivers/crypto/hisilicon/hpre/hpre_main.c:73: note: this is the location of the previous definition 73 | #define HPRE_QM_AXI_CFG_MASK 0xffff | >> drivers/crypto/hisilicon/hpre/hpre_main.c:80: warning: "HPRE_QM_VFG_AX_MASK" redefined 80 | #define HPRE_QM_VFG_AX_MASK GENMASK(7, 0) | drivers/crypto/hisilicon/hpre/hpre_main.c:74: note: this is the location of the previous definition 74 | #define HPRE_QM_VFG_AX_MASK 0xff | >> drivers/crypto/hisilicon/hpre/hpre_main.c:81: warning: "HPRE_BD_USR_MASK" redefined 81 | #define HPRE_BD_USR_MASK GENMASK(1, 0) | drivers/crypto/hisilicon/hpre/hpre_main.c:75: note: this is the location of the previous definition 75 | #define HPRE_BD_USR_MASK 0x3 | >> drivers/crypto/hisilicon/hpre/hpre_main.c:82: warning: "HPRE_CLUSTER_CORE_MASK_V2" redefined 82 | #define HPRE_CLUSTER_CORE_MASK_V2 GENMASK(3, 0) | drivers/crypto/hisilicon/hpre/hpre_main.c:76: note: this is the location of the previous definition 76 | #define HPRE_CLUSTER_CORE_MASK_V2 0xf | >> drivers/crypto/hisilicon/hpre/hpre_main.c:83: warning: "HPRE_CLUSTER_CORE_MASK_V3" redefined 83 | #define HPRE_CLUSTER_CORE_MASK_V3 GENMASK(7, 0) | drivers/crypto/hisilicon/hpre/hpre_main.c:77: note: this is the location of the previous definition 77 | #define HPRE_CLUSTER_CORE_MASK_V3 0xff | vim +/HPRE_QM_USR_CFG_MASK +78 drivers/crypto/hisilicon/hpre/hpre_main.c 54 55 #define HPRE_CORE_ENB (HPRE_CLSTR_BASE + HPRE_CORE_EN_OFFSET) 56 #define HPRE_CORE_INI_CFG (HPRE_CLSTR_BASE + HPRE_CORE_INI_CFG_OFFSET) 57 #define HPRE_CORE_INI_STATUS (HPRE_CLSTR_BASE + HPRE_CORE_INI_STATUS_OFFSET) 58 #define HPRE_HAC_ECC1_CNT 0x301a04 59 #define HPRE_HAC_ECC2_CNT 0x301a08 60 #define HPRE_HAC_INT_STATUS 0x301800 61 #define HPRE_HAC_SOURCE_INT 0x301600 62 #define HPRE_CLSTR_ADDR_INTRVL 0x1000 63 #define HPRE_CLUSTER_INQURY 0x100 64 #define HPRE_CLSTR_ADDR_INQRY_RSLT 0x104 65 #define HPRE_TIMEOUT_ABNML_BIT 6 66 #define HPRE_PASID_EN_BIT 9 67 #define HPRE_REG_RD_INTVRL_US 10 68 #define HPRE_REG_RD_TMOUT_US 1000 69 #define HPRE_DBGFS_VAL_MAX_LEN 20 70 #define HPRE_PCI_DEVICE_ID 0xa258 71 #define HPRE_PCI_VF_DEVICE_ID 0xa259 72 #define HPRE_QM_USR_CFG_MASK 0xfffffffe 73 #define HPRE_QM_AXI_CFG_MASK 0xffff 74 #define HPRE_QM_VFG_AX_MASK 0xff 75 #define HPRE_BD_USR_MASK 0x3 76 #define HPRE_CLUSTER_CORE_MASK_V2 0xf 77 #define HPRE_CLUSTER_CORE_MASK_V3 0xff > 78 #define HPRE_QM_USR_CFG_MASK GENMASK(31, 1) > 79 #define HPRE_QM_AXI_CFG_MASK GENMASK(15, 0) > 80 #define HPRE_QM_VFG_AX_MASK GENMASK(7, 0) > 81 #define HPRE_BD_USR_MASK GENMASK(1, 0) > 82 #define HPRE_CLUSTER_CORE_MASK_V2 GENMASK(3, 0) > 83 #define HPRE_CLUSTER_CORE_MASK_V3 GENMASK(7, 0) 84 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx
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