On Thu, Nov 26, 2020 at 11:51:46AM +0000, Daniele Alessandrelli wrote: > The Intel Keem Bay SoC has an Offload Crypto Subsystem (OCS) featuring a > crypto engine for accelerating AES/SM4 operations. > > This driver adds support for such hardware thus enabling hardware > acceleration for the following transformations on the Intel Keem Bay SoC: > > - ecb(aes), cbc(aes), ctr(aes), cts(cbc(aes)), gcm(aes) and cbc(aes); > supported for 128-bit and 256-bit keys. > > - ecb(sm4), cbc(sm4), ctr(sm4), cts(cbc(sm4)), gcm(sm4) and cbc(sm4); > supported for 128-bit keys. > > The driver passes crypto manager self-tests, including the extra tests > (CRYPTO_MANAGER_EXTRA_TESTS=y). > > Note: this driver is different from the Keem Bay OCS HCU driver previously > submitted. Keem Bay OCS HCU provides hardware-accelerated ahash, while > Keem Bay AES/SM4 (i.e., this driver) provides hardware-accelerated > skcipher and aead. > > > Daniele Alessandrelli (1): > dt-bindings: Add Keem Bay OCS AES bindings > > Mike Healy (1): > crypto: keembay-ocs-aes: Add support for Keem Bay OCS AES/SM4 > > .../crypto/intel,keembay-ocs-aes.yaml | 45 + > MAINTAINERS | 10 + > drivers/crypto/Kconfig | 2 + > drivers/crypto/Makefile | 1 + > drivers/crypto/keembay/Kconfig | 39 + > drivers/crypto/keembay/Makefile | 5 + > drivers/crypto/keembay/keembay-ocs-aes-core.c | 1713 +++++++++++++++++ > drivers/crypto/keembay/ocs-aes.c | 1489 ++++++++++++++ > drivers/crypto/keembay/ocs-aes.h | 129 ++ > 9 files changed, 3433 insertions(+) > create mode 100644 Documentation/devicetree/bindings/crypto/intel,keembay-ocs-aes.yaml > create mode 100644 drivers/crypto/keembay/Kconfig > create mode 100644 drivers/crypto/keembay/Makefile > create mode 100644 drivers/crypto/keembay/keembay-ocs-aes-core.c > create mode 100644 drivers/crypto/keembay/ocs-aes.c > create mode 100644 drivers/crypto/keembay/ocs-aes.h All applied. Thanks. -- Email: Herbert Xu <herbert@xxxxxxxxxxxxxxxxxxx> Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
