Add the wake up event to chip info since this value will be different
in the next generation of QAT devices.
Signed-off-by: Jack Xu <jack.xu@xxxxxxxxx>
Co-developed-by: Wojciech Ziemba <wojciech.ziemba@xxxxxxxxx>
Signed-off-by: Wojciech Ziemba <wojciech.ziemba@xxxxxxxxx>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@xxxxxxxxx>
---
drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h | 1 +
drivers/crypto/qat/qat_common/icp_qat_hal.h | 1 +
drivers/crypto/qat/qat_common/qat_hal.c | 5 ++++-
3 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h b/drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h
index 1d6ab3407dc9..090c3e73938c 100644
--- a/drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h
+++ b/drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h
@@ -30,6 +30,7 @@ struct icp_qat_fw_loader_chip_info {
u32 icp_rst_csr;
u32 icp_rst_mask;
u32 glb_clk_enable_csr;
+ u32 wakeup_event_val;
bool fw_auth;
};
diff --git a/drivers/crypto/qat/qat_common/icp_qat_hal.h b/drivers/crypto/qat/qat_common/icp_qat_hal.h
index 82ac33a4500f..b3aa4c8a3ba8 100644
--- a/drivers/crypto/qat/qat_common/icp_qat_hal.h
+++ b/drivers/crypto/qat/qat_common/icp_qat_hal.h
@@ -87,6 +87,7 @@ enum fcu_sts {
#define XCWE_VOLUNTARY (0x1)
#define LCS_STATUS (0x1)
#define MMC_SHARE_CS_BITPOS 2
+#define WAKEUP_EVENT 0x10000
#define FCU_CTRL_AE_POS 0x8
#define FCU_AUTH_STS_MASK 0x7
#define FCU_STS_DONE_POS 0x9
diff --git a/drivers/crypto/qat/qat_common/qat_hal.c b/drivers/crypto/qat/qat_common/qat_hal.c
index 6e6bca281ab7..c073e4e3e3ae 100644
--- a/drivers/crypto/qat/qat_common/qat_hal.c
+++ b/drivers/crypto/qat/qat_common/qat_hal.c
@@ -702,6 +702,7 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG;
handle->chip_info->icp_rst_csr = ICP_RESET;
handle->chip_info->glb_clk_enable_csr = ICP_GLOBAL_CLK_ENABLE;
+ handle->chip_info->wakeup_event_val = WAKEUP_EVENT;
handle->chip_info->fw_auth = true;
break;
case PCI_DEVICE_ID_INTEL_QAT_DH895XCC:
@@ -711,6 +712,7 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG;
handle->chip_info->icp_rst_csr = ICP_RESET;
handle->chip_info->glb_clk_enable_csr = ICP_GLOBAL_CLK_ENABLE;
+ handle->chip_info->wakeup_event_val = WAKEUP_EVENT;
handle->chip_info->fw_auth = false;
break;
default:
@@ -834,6 +836,7 @@ void qat_hal_deinit(struct icp_qat_fw_loader_handle *handle)
int qat_hal_start(struct icp_qat_fw_loader_handle *handle)
{
unsigned long ae_mask = handle->hal_handle->ae_mask;
+ u32 wakeup_val = handle->chip_info->wakeup_event_val;
unsigned int fcu_sts;
unsigned char ae;
u32 ae_ctr = 0;
@@ -852,7 +855,7 @@ int qat_hal_start(struct icp_qat_fw_loader_handle *handle)
return 0;
} else {
for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {
- qat_hal_put_wakeup_event(handle, ae, 0, 0x10000);
+ qat_hal_put_wakeup_event(handle, ae, 0, wakeup_val);
qat_hal_enable_ctx(handle, ae, ICP_QAT_UCLO_AE_ALL_CTX);
ae_ctr++;
}
--
2.25.4
