On Fri, Sep 18, 2020 at 07:42:35AM +0000, Van Leeuwen, Pascal wrote: > > Actually, that is what we did as a _quick hack_ initially, but: > > First of all, it's not only about the L1 cacheline size. It's about the worst case cache > line size in the path all the way from the CPU to the actual memory interface. > > Second, cache line sizes may differ from system to system. So it's not actually > a constant at all (unless you compile the driver specifically for 1 target system). Can this alignment exceed ARCH_DMA_MINALIGN? If not then the macro CRYPTO_MINALIGN should cover it. Cheers, -- Email: Herbert Xu <herbert@xxxxxxxxxxxxxxxxxxx> Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
