On 2020/8/2 22:52, Jia-Ju Bai wrote: > In qm_qp_ctx_cfg(), "sqc" and "aeqc" are mapped to streaming DMA: > eqc_dma = dma_map_single(..., eqc, ...); > ...... > aeqc_dma = dma_map_single(..., aeqc, ...); Only sqc, cqc will be configured in qm_qp_ctx_cfg. > > Then "sqc" and "aeqc" are accessed at many places, such as: > eqc->base_l = cpu_to_le32(lower_32_bits(qm->eqe_dma)); > eqc->base_h = cpu_to_le32(upper_32_bits(qm->eqe_dma)); > ...... > aeqc->base_l = cpu_to_le32(lower_32_bits(qm->aeqe_dma)); > aeqc->base_h = cpu_to_le32(upper_32_bits(qm->aeqe_dma)); There are sqc, cqc, eqc, aeqc, you seems misunderstand them. > > These accesses may cause data inconsistency between CPU cache and hardware. > > I am not sure how to properly fix this problem, and thus I only report it. In qm_qp_ctx_cfg, sqc/cqc memory will be allocated and related mailbox will be sent to hardware. In qm_eq_ctx_cfg, eqc/aeqc related operations will be done. So there is no problem here :) Thanks, Zhou > > > Best wishes, > Jia-Ju Bai > >
