Haren Myneni <haren@xxxxxxxxxxxxxxxxxx> writes:
>
> System gets checkstop if RxFIFO overruns with more requests than the
> maximum possible number of CRBs in FIFO at the same time. So find max
> CRBs from FIFO size and set it to receive window credits.
>
> CC: stable@xxxxxxxxxxxxxxx # v4.14+
> Signed-off-by:Haren Myneni <haren@xxxxxxxxxx>
It's helpful to mention the actual commit that's fixed, so that people
with backports can join things up, so should that be:
Fixes: b0d6c9bab5e4 ("crypto/nx: Add P9 NX support for 842 compression engine")
???
cheers
> diff --git a/drivers/crypto/nx/nx-842-powernv.c b/drivers/crypto/nx/nx-842-powernv.c
> index 4acbc47..e78ff5c 100644
> --- a/drivers/crypto/nx/nx-842-powernv.c
> +++ b/drivers/crypto/nx/nx-842-powernv.c
> @@ -27,8 +27,6 @@
> #define WORKMEM_ALIGN (CRB_ALIGN)
> #define CSB_WAIT_MAX (5000) /* ms */
> #define VAS_RETRIES (10)
> -/* # of requests allowed per RxFIFO at a time. 0 for unlimited */
> -#define MAX_CREDITS_PER_RXFIFO (1024)
>
> struct nx842_workmem {
> /* Below fields must be properly aligned */
> @@ -812,7 +810,11 @@ static int __init vas_cfg_coproc_info(struct device_node *dn, int chip_id,
> rxattr.lnotify_lpid = lpid;
> rxattr.lnotify_pid = pid;
> rxattr.lnotify_tid = tid;
> - rxattr.wcreds_max = MAX_CREDITS_PER_RXFIFO;
> + /*
> + * Maximum RX window credits can not be more than #CRBs in
> + * RxFIFO. Otherwise, can get checkstop if RxFIFO overruns.
> + */
> + rxattr.wcreds_max = fifo_size / CRB_SIZE;
>
> /*
> * Open a VAS receice window which is used to configure RxFIFO
