On Mon, Jun 17, 2019 at 12:24 PM Leonard Crestez <leonard.crestez@xxxxxxx> wrote: > > On 6/17/2019 7:04 PM, Andrey Smirnov wrote: > > From: Chris Spencer <christopher.spencer@xxxxxxxxx> > > > > The i.MX8 is arm64, but its CAAM DMA address size is 32-bits. > > > +/* > > + * On i.MX8 boards the arch is arm64 but the CAAM dma address size is > > + * 32 bits on 8MQ and 36 bits on 8QM and 8QXP. > > + * For 8QM and 8QXP there is a configurable field PS called pointer size > > + * in the MCFGR register to switch between 32 and 64 (default 32) > > + * But this register is only accessible by the SECO and is left to its > > + * default value. > > + * Here we set the CAAM dma address size to 32 bits for all i.MX8 > > + */ > > +#if defined(CONFIG_ARM64) && defined(CONFIG_ARCH_MXC) > > +#define caam_dma_addr_t u32 > > +#else > > +#define caam_dma_addr_t dma_addr_t > > +#endif > > Wait, doesn't this break Layerscape? Support for multiple SOC families > can be enabled at the same time and it is something that we actually > want to support. > Ugh, l think you are right. Will fix in next version. Thanks, Andrey Smirnov
