On 12/21/17 9:51 AM, Brijesh Singh wrote: > > On 12/21/17 7:06 AM, Paolo Bonzini wrote: > .... > > Hi Paolo, > > >> Hi Brijesh, >> >> I have a couple comments: >> >> 1) how is MSR_AMD64_SEV's value passed to the guest, and where is it in >> the manual? > It is a non interceptable read-only MSR set by the HW when SEV feature > is enabled in VMRUN instruction. I just checked both PPR and Family 17 manual and it seems both are still missing this MSR definition. I will ping doc team to get it updated. thanks >> 2) ECX should be 0 in the guest's 0x8000_001f leaf, because we don't >> support nested SEV guests. Likewise, EAX bit 2 should be 0 since you >> don't emulate the page flush MSR. > IIRC, I do clear both EAX Page_Flush and nested virtualization case from > Qemu SEV feature is enabled. >> Both can be fixed on top (and I can do the second myself of course), so >> there should be no need for a v10. > Thanks >
