On Mon, Jun 19, 2017 at 03:23:41AM -0700, Frank Rowand wrote: > On 06/18/17 07:05, Rob Herring wrote: > > On Tue, Jun 13, 2017 at 07:49:04PM -0700, frowand.list@xxxxxxxxx wrote: > >> From: Frank Rowand <frank.rowand@xxxxxxxx> > >> > >> The Devicetree Specification has superseded the ePAPR as the > >> base specification for bindings. Update files in Documentation > >> to reference the new document. > >> > >> Some files are not updated because there is no hypervisor chapter > >> in the Devicetree Specification: > >> Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt > >> Documenation/virtual/kvm/api.txt > >> Documenation/virtual/kvm/ppc-pv.txt > >> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt > >> index f8cd2397aa04..d63ab1dec16d 100644 > >> --- a/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt > >> +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt > >> @@ -3,10 +3,10 @@ Power Architecture CPU Binding > >> Copyright 2013 Freescale Semiconductor Inc. > >> > >> Power Architecture CPUs in Freescale SOCs are represented in device trees as > >> -per the definition in ePAPR. > >> +per the definition in the Devicetree Specification. > > > > Are we sure we didn't remove any PPC specifics that apply here? > > I don't see any. > > Table 3.7.1 "General Properties of CPU nodes" was slightly > re-ordered, but the same properties are listed in both documents. > > I don't think that the boot requirements removal impacts this > file. > > Am I missing something? No, I just wanted to make sure. So I guess there's just that one minor thing to drop. Rob
