Hi Maxime, On Mon, May 29, 2017 at 10:29:31AM +0200, Maxime Ripard wrote: > On Mon, May 29, 2017 at 10:09:44AM +0200, Antoine Tenart wrote: > > > Which speed are the SS clocks ? > > > > The AHB SS clk is running at 300 MHz and the SS clk at 150 MHz. SS clk > > is at the expected rate but the AHB SS clk has a higher rate that what's > > expected. > > > > In the probing function only the SS clk rate is explicitly set. I tried > > to set the AHB clk rate as well and removed the delays. This didn't fix > > the framework selftests at boot time. Is there any reason the AHB SS clk > > rate isn't explicitly set when probing the driver? (Should it?) > > It probably shouldn't. > > The AHB clock is shared by most of the drivers, some of them actually > using that clock to generate their signals. > > You would have to unbreak all those drivers first, which is probably > not needed at all. I haven't seen a case where a block had a module > clock and did care for its AHB clock rate. OK, makes sense. I'll wait for Corentin to test the series, and I'll send a v2 only fixing the typos then. Thanks! Antoine -- Antoine Ténart, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
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