Hi Igal,
On Mon, Apr 24, 2017 at 08:50:32AM +0000, Igal Liberman wrote:
> [...]
>
> > + priv->clk = of_clk_get(dev->of_node, 0);
> > + if (!IS_ERR(priv->clk)) {
> > + ret = clk_prepare_enable(priv->clk);
> > + if (ret) {
> > + dev_err(dev, "unable to enable clk (%d)\n", ret);
> > + return ret;
> > + }
> > + } else {
> > + /* The clock isn't mandatory */
> > + if (PTR_ERR(priv->clk) == -EPROBE_DEFER)
> > + return -EPROBE_DEFER;
> > + }
> > +
> > + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
>
> The correct address width of the engine in Marvell SoCs is 40bit.
Oops. I'll update.
Thanks!
Antoine
--
Antoine Ténart, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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