RE: [PATCH] crypto: qat - fix CTX_ENABLES bits shift direction issue

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There is no very strong reason, but I think 0xff << CE_ENABLE_BITPOS is more clearly for reading,
So that we can clearly know we are accessing the 8 CTXs in CTX_ENABLES CSR 8-15 bits.

Best Regards,
Pingchao yang


-----Original Message-----
From: walter harms [mailto:wharms@xxxxxx] 
Sent: Wednesday, December 16, 2015 4:10 PM
To: Yang, Pingchao
Cc: herbert@xxxxxxxxxxxxxxxxxxx; dan.carpenter@xxxxxxxxxx; Struk, Tadeusz; linux-crypto@xxxxxxxxxxxxxxx; qat-linux; kernel-janitors@xxxxxxxxxxxxxxx
Subject: Re: [PATCH] crypto: qat - fix CTX_ENABLES bits shift direction issue



Am 16.12.2015 03:39, schrieb Yang Pingchao:
> AE CTX bits should be 8-15 in CTX_ENABLES, so the mask value 0xff 
> should be left shifted 0x8.
> 
> Reported-by: Dan Carpenter <dan.carpenter@xxxxxxxxxx>
> Signed-off-by: Yang Pingchao <pingchao.yang@xxxxxxxxx>
> ---
>  drivers/crypto/qat/qat_common/qat_hal.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/crypto/qat/qat_common/qat_hal.c 
> b/drivers/crypto/qat/qat_common/qat_hal.c
> index 45c1739..81bd1fe 100644
> --- a/drivers/crypto/qat/qat_common/qat_hal.c
> +++ b/drivers/crypto/qat/qat_common/qat_hal.c
> @@ -418,7 +418,7 @@ int qat_hal_check_ae_active(struct 
> icp_qat_fw_loader_handle *handle,
>  
>  	qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &enable);
>  	qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS, &active);
> -	if ((enable & (0xff >> CE_ENABLE_BITPOS)) ||
> +	if ((enable & (0xff << CE_ENABLE_BITPOS)) ||
>  	    (active & (1 << ACS_ABO_BITPOS)))
>  		return 1;
>  	else

Is there any reason for using 0xff << CE_ENABLE_BITPOS instead of 0xff00 ?

re,
 wh
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