Hi Kim > -----Original Message----- > From: Kim Phillips [mailto:kim.phillips@xxxxxxxxxxxxx] > Sent: Thursday, June 12, 2014 4:23 AM > To: Gupta Ruchika-R66431 > Cc: linux-crypto@xxxxxxxxxxxxxxx; herbert@xxxxxxxxxxxxxxxxxxx > Subject: Re: [PATCH] crypto:caam - Modify width of few read only registers > > On Tue, 29 Apr 2014 15:34:37 +0530 > Ruchika Gupta <ruchika.gupta@xxxxxxxxxxxxx> wrote: > > > Few read only registers like CHAVID, CTPR etc were wrongly defined as > > 64 bit registers. This functioned properly on the powerpc platforms. > > However ARM SoC's wouldn't function correctly if these registers are > > defined as 64 bit. So correcting the definition to two 32 bit registers. > > please rewrite, adding the details of the problem posted toward the end of > this thread, e.g., what registers are affected, and how that renders > MCFGR:DWT ineffective in this case. Ok. I will add the details in the commit message. > > > /* Check to see if QI present. If so, enable */ > > - ctrlpriv->qi_present = !!(rd_reg64(&topregs->ctrl.perfmon.comp_parms) & > > - CTPR_QI_MASK); > > + ctrlpriv->qi_present = > > + !!(rd_reg32(&topregs->ctrl.perfmon.comp_parms_ms) & > > + CTPR_MS_QI_MASK); > > alignment Ok. I will correct it. > > > /* Report "alive" for developer to see */ > > - dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id, > > + dev_info(dev, "device ID = 0x%08x (Era %d)\n", caam_id, > > caam_get_era()); > > Why are we dropping the upper 32 bits here? The upper 32 bit contain the IP ID of SEC, the major number and the minor number while the lower 32 bits have the details of the compile option, integration and configuration options of SEC. So device ID is actually contained only in the most significant 32 bits which are being printed here. Ruchika > > Kim -- To unsubscribe from this list: send the line "unsubscribe linux-crypto" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
