> -----Original Message----- > From: Kim Phillips [mailto:kim.phillips@xxxxxxxxxxxxx] > Sent: Friday, May 02, 2014 2:15 AM > To: Gupta Ruchika-R66431 > Cc: linux-crypto@xxxxxxxxxxxxxxx; herbert@xxxxxxxxxxxxxxxxxxx > Subject: Re: [PATCH] crypto:caam - Modify width of few read only registers > > On Tue, 29 Apr 2014 15:34:37 +0530 > Ruchika Gupta <ruchika.gupta@xxxxxxxxxxxxx> wrote: > > > Few read only registers like CHAVID, CTPR etc were wrongly defined as > > 64 bit registers. This functioned properly on the powerpc platforms. > > However ARM SoC's wouldn't function correctly if these registers are > > defined as 64 bit. > > why wouldn't they function correctly? The SEC IP guide states these registers as 2 32 bit registers. So register definition in crypto code should also have them defined as 32 bit registers. Defining them as 64 bit in this case would be incorrect. Endianness of the CAAM IP varies with core's endiannes. In ARM SoC's , CAAM block is also little endian. So in case the 2 - 32 bit registers are treated as a 64 bit register, the result would be word swapped as compared to powerpc platforms. As a result, the reads won't return the right result. For eg. For the 2 32 bit registers CHAVID_MS(at address 0x0) and CHAVID_LS(address 0x4) , if core reads them as 64 bit word, In powerpc (big endian) platform - CHAVID_MS would be available in most significant portion of the 64 bit word. CHAVID_LS would be the in least significant portion. This is as expected. In ARM (little endian) platform, 64 bit read would result in - CHAVID_MS in Least significant portion of the word and CHAVID_LS in the most significant location. This result is word swapped and the value read wouldn't be correct. Ruchika > > Kim -- To unsubscribe from this list: send the line "unsubscribe linux-crypto" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
